{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,7]],"date-time":"2026-06-07T12:59:40Z","timestamp":1780837180459,"version":"3.54.1"},"reference-count":21,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Computers and Electrical Engineering"],"published-print":{"date-parts":[[2026,9]]},"DOI":"10.1016\/j.compeleceng.2026.111270","type":"journal-article","created":{"date-parts":[[2026,5,30]],"date-time":"2026-05-30T04:18:58Z","timestamp":1780114738000},"page":"111270","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["A Novel Design Paradigm of Arbitrary R2-Parallel Pipelined, Radix-R Constant Rotator FFT Architectures"],"prefix":"10.1016","volume":"137","author":[{"given":"Vijay Moni","family":"Varghese","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kumaravel","family":"S.","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"78","reference":[{"key":"10.1016\/j.compeleceng.2026.111270_b1","article-title":"Enhancing flexibility and system performance in 6G and beyond: A user-based numerology and waveform approach","author":"Sayed","year":"2024","journal-title":"Digit Commun Netw"},{"issue":"10","key":"10.1016\/j.compeleceng.2026.111270_b2","first-page":"4004","article-title":"Low-latency 64-parallel 4096-point memory-based FFT for 6G","volume":"70","author":"Kaya","year":"2023","journal-title":"IEEE Trans Circuits Syst I: Regul Pap"},{"issue":"2","key":"10.1016\/j.compeleceng.2026.111270_b3","doi-asserted-by":"crossref","first-page":"219","DOI":"10.1109\/TVLSI.2022.3227346","article-title":"A 60-mode high-throughput parallel-processing FFT processor for 5G\/4G applications","volume":"31","author":"Guo","year":"2023","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"10.1016\/j.compeleceng.2026.111270_b4","doi-asserted-by":"crossref","unstructured":"Chan C-K, Lin H-K, Liu C-W. High-Throughput 64K-point FFT Processor for THz Imaging Radar System. In: 2019 international symposium on VLSI design, automation and test. VLSI-DAT, Hsinchu, Taiwan; 2019, p. 1\u20134. http:\/\/dx.doi.org\/10.1109\/VLSI-DAT.2019.8741687.","DOI":"10.1109\/VLSI-DAT.2019.8741687"},{"issue":"8","key":"10.1016\/j.compeleceng.2026.111270_b5","doi-asserted-by":"crossref","first-page":"3044","DOI":"10.1109\/TMI.2024.3383466","article-title":"SASAN: Spectrum-axial spatial approach networks for medical image segmentation","volume":"43","author":"Huang","year":"2024","journal-title":"IEEE Trans Med Imaging"},{"key":"10.1016\/j.compeleceng.2026.111270_b6","doi-asserted-by":"crossref","DOI":"10.1109\/TIM.2023.3301891","article-title":"An efficient implementation approach to FFT processor for spectral analysis","volume":"72","author":"Hazarika","year":"2023","journal-title":"IEEE Trans Instrum Meas"},{"key":"10.1016\/j.compeleceng.2026.111270_b7","series-title":"IBM quantum computing blog","article-title":"Celebrating the FFT and the future of computing","author":"IBM Quantum","year":"2025"},{"issue":"8","key":"10.1016\/j.compeleceng.2026.111270_b8","first-page":"3084","article-title":"Memory-based FFT architecture with optimized number of multiplexers and memory usage","volume":"70","author":"Kaya","year":"2023","journal-title":"IEEE Trans Circuits Syst II: Express Briefs"},{"key":"10.1016\/j.compeleceng.2026.111270_b9","series-title":"2023 38th conference on design of circuits and integrated systems","article-title":"An automatic generator of non-power-of-two SDF FFT architectures for 5G and beyond","author":"Bautista","year":"2023"},{"issue":"11","key":"10.1016\/j.compeleceng.2026.111270_b10","doi-asserted-by":"crossref","first-page":"1345","DOI":"10.1007\/s11265-021-01655-1","article-title":"A survey on pipelined FFT hardware architectures","volume":"94","author":"Garrido","year":"2022","journal-title":"J Signal Process Syst"},{"issue":"4","key":"10.1016\/j.compeleceng.2026.111270_b11","doi-asserted-by":"crossref","first-page":"1507","DOI":"10.1109\/TCSI.2018.2886626","article-title":"World\u2019s fastest FFT architectures: Breaking the barrier of 100 GS\/s","volume":"66","author":"Garrido","year":"2018","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"issue":"7","key":"10.1016\/j.compeleceng.2026.111270_b12","doi-asserted-by":"crossref","first-page":"2002","DOI":"10.1109\/TCSI.2014.2304664","article-title":"Low-complexity multiplierless constant rotators based on combined coefficient selection and shift-and-add implementation (CCSSI)","volume":"61","author":"Garrido","year":"2014","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"issue":"1","key":"10.1016\/j.compeleceng.2026.111270_b13","doi-asserted-by":"crossref","first-page":"322","DOI":"10.1109\/TCSI.2020.3031688","article-title":"The constant multiplier FFT","volume":"68","author":"Garrido","year":"2020","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"issue":"6","key":"10.1016\/j.compeleceng.2026.111270_b14","doi-asserted-by":"crossref","first-page":"3646","DOI":"10.1002\/cta.4305","article-title":"Design of high-performance radix-power-of-2 butterfly architectures for FFT implementation by cosine coefficients extraction","volume":"53","author":"Moni Varghese","year":"2025","journal-title":"Int J Circuit Theory Appl"},{"issue":"5","key":"10.1016\/j.compeleceng.2026.111270_b15","doi-asserted-by":"crossref","first-page":"1148","DOI":"10.1109\/TVLSI.2019.2892322","article-title":"Optimum circuits for bit-dimension permutations","volume":"27","author":"Garrido","year":"2019","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"key":"10.1016\/j.compeleceng.2026.111270_b16","series-title":"2024 IEEE Asia pacific conference on circuits and systems","first-page":"183","article-title":"A 250.3\u03bcW versatile sound feature extractor using 1024-point FFT 64-ch LogMel filter in 40 nm CMOS","author":"Kawada","year":"2024"},{"key":"10.1016\/j.compeleceng.2026.111270_b17","doi-asserted-by":"crossref","DOI":"10.1016\/j.mejo.2021.105276","article-title":"A low-power twiddle factor addressing architecture for split-radix FFT processor","volume":"117","author":"Liu","year":"2021","journal-title":"Microelectron J"},{"key":"10.1016\/j.compeleceng.2026.111270_b18","series-title":"2019 national conference on communications","article-title":"High performance multiplierless serial pipelined VLSI architecture for real-valued FFT","author":"Hazarika","year":"2019"},{"issue":"6","key":"10.1016\/j.compeleceng.2026.111270_b19","doi-asserted-by":"crossref","first-page":"461","DOI":"10.1049\/iet-cdt.2019.0025","article-title":"Energy efficient VLSI architecture of real-valued serial pipelined FFT","volume":"13","author":"Hazarika","year":"2019","journal-title":"IET Comput Digit Tech"},{"issue":"10","key":"10.1016\/j.compeleceng.2026.111270_b20","doi-asserted-by":"crossref","first-page":"3291","DOI":"10.1109\/TCSI.2018.2831007","article-title":"An area efficient 1024-point low power radix-2 2 FFT processor with feed-forward multiple delay commutators","volume":"65","author":"Le Ba","year":"2018","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"issue":"2","key":"10.1016\/j.compeleceng.2026.111270_b21","doi-asserted-by":"crossref","first-page":"219","DOI":"10.1109\/TVLSI.2022.3227346","article-title":"A 60-mode high-throughput parallel-processing FFT processor for 5G\/4G applications","volume":"31","author":"Guo","year":"2023","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"}],"container-title":["Computers and Electrical Engineering"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0045790626003423?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0045790626003423?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,6,7]],"date-time":"2026-06-07T12:24:33Z","timestamp":1780835073000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0045790626003423"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,9]]},"references-count":21,"alternative-id":["S0045790626003423"],"URL":"https:\/\/doi.org\/10.1016\/j.compeleceng.2026.111270","relation":{},"ISSN":["0045-7906"],"issn-type":[{"value":"0045-7906","type":"print"}],"subject":[],"published":{"date-parts":[[2026,9]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A Novel Design Paradigm of Arbitrary -Parallel Pipelined, Radix- Constant Rotator FFT Architectures","name":"articletitle","label":"Article Title"},{"value":"Computers and Electrical Engineering","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.compeleceng.2026.111270","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Elsevier Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}],"article-number":"111270"}}