{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,4]],"date-time":"2026-07-04T01:23:43Z","timestamp":1783128223545,"version":"3.54.6"},"reference-count":33,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62072354"],"award-info":[{"award-number":["62072354"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62167009"],"award-info":[{"award-number":["62167009"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100019282","name":"Yulin University","doi-asserted-by":"publisher","award":["22GK04"],"award-info":[{"award-number":["22GK04"]}],"id":[{"id":"10.13039\/501100019282","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Future Generation Computer Systems"],"published-print":{"date-parts":[[2026,10]]},"DOI":"10.1016\/j.future.2026.108565","type":"journal-article","created":{"date-parts":[[2026,5,9]],"date-time":"2026-05-09T23:07:23Z","timestamp":1778368043000},"page":"108565","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["Unified processing-in-memory for ultrasound imaging: A dual-kernel memristor architecture with pipeline-aware scheduling"],"prefix":"10.1016","volume":"183","author":[{"ORCID":"https:\/\/orcid.org\/0009-0003-6814-5070","authenticated-orcid":false,"given":"Junjie","family":"Wang","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7385-032X","authenticated-orcid":false,"given":"Zhao","family":"Huang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7657-0945","authenticated-orcid":false,"given":"Ping","family":"Jiang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0726-3164","authenticated-orcid":false,"given":"Gang","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yuning","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lihui","family":"Xu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"YunFeng","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"78","reference":[{"issue":"1","key":"10.1016\/j.future.2026.108565_b1","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1145\/216585.216588","article-title":"Hitting the memory wall: Implications of the obvious","volume":"23","author":"Wulf","year":"1995","journal-title":"ACM SIGARCH Comput. Archit. News"},{"issue":"6","key":"10.1016\/j.future.2026.108565_b2","article-title":"A survey of task scheduling algorithms for heterogeneous computing systems","volume":"55","author":"Akash","year":"2022","journal-title":"ACM Comput. Surv."},{"key":"10.1016\/j.future.2026.108565_b3","doi-asserted-by":"crossref","first-page":"28","DOI":"10.1016\/j.micpro.2019.01.009","article-title":"Processing data where it makes sense: enabling in-memory computation","volume":"67","author":"Mutlu","year":"2019","journal-title":"Microprocessors and Microsystems","ISSN":"https:\/\/id.crossref.org\/issn\/0141-9331","issn-type":"print"},{"issue":"3","key":"10.1016\/j.future.2026.108565_b4","doi-asserted-by":"crossref","first-page":"14","DOI":"10.1145\/3007787.3001139","article-title":"Isaac: A convolutional neural network accelerator with in-situ analog arithmetic in crossbars","volume":"44","author":"Shafiee","year":"2016","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"10.1016\/j.future.2026.108565_b5","series-title":"2018 IEEE International Solid-State Circuits Conference (ISSCC)","first-page":"496","article-title":"A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS\/W fully parallel product-sum operation for binary DNN edge processors","author":"Khwa","year":"2018"},{"issue":"1","key":"10.1016\/j.future.2026.108565_b6","first-page":"45","article-title":"Activity-difference training of deep neural networks using memristor crossbars","volume":"6","author":"i. Yi","year":"2023","journal-title":"Nat. Electron."},{"key":"10.1016\/j.future.2026.108565_b7","series-title":"2016 53nd acm\/edac\/ieee Design Automation Conference","first-page":"1","article-title":"Dot-product engine for neuromorphic computing: Programming 1t1m crossbar to accelerate matrix\u2013vector multiplication","author":"Hu","year":"2016"},{"key":"10.1016\/j.future.2026.108565_b8","series-title":"2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium","first-page":"1","article-title":"Aepe: An area and power efficient rram crossbar-based accelerator for deep cnns","author":"Tang","year":"2017"},{"key":"10.1016\/j.future.2026.108565_b9","doi-asserted-by":"crossref","DOI":"10.1587\/elex.17.20200005","article-title":"Dm-imca: A dual-mode in-memory computing architecture for general purpose processing","author":"Zeng","year":"2020","journal-title":"IEICE Electron. Express"},{"key":"10.1016\/j.future.2026.108565_b10","doi-asserted-by":"crossref","first-page":"69327","DOI":"10.1109\/ACCESS.2020.2986513","article-title":"Single crossbar array of memristors with bipolar inputs for neuromorphic image recognition","volume":"8","author":"Truong","year":"2020","journal-title":"IEEE Access"},{"key":"10.1016\/j.future.2026.108565_b11","series-title":"A reconfigurable fir filter with memristor-based weights","author":"Bayat","year":"2016"},{"issue":"3","key":"10.1016\/j.future.2026.108565_b12","doi-asserted-by":"crossref","first-page":"529","DOI":"10.1007\/s10470-014-0275-3","article-title":"Programmable discrete-time type i and type ii fir filter design on the memristor crossbar structure","volume":"79","author":"Mirebrahimi","year":"2014","journal-title":"Analog Integr. Circuits Signal Process."},{"issue":"6","key":"10.1016\/j.future.2026.108565_b13","doi-asserted-by":"crossref","first-page":"1104","DOI":"10.1109\/TNANO.2015.2473666","article-title":"New twin crossbar architecture of binary memristors for low-power image recognition with discrete cosine transform","volume":"14","author":"Truong","year":"2015","journal-title":"IEEE Trans. Nanotechnol."},{"key":"10.1016\/j.future.2026.108565_b14","series-title":"2017 IEEE International Symposium on High Performance Computer Architecture","first-page":"541","article-title":"Pipelayer: A pipelined reram-based accelerator for deep learning","author":"Song","year":"2017"},{"key":"10.1016\/j.future.2026.108565_b15","series-title":"Neupims: npu-pim heterogeneous acceleration for batched llm inferencing","author":"Heo","year":"2024"},{"key":"10.1016\/j.future.2026.108565_b16","doi-asserted-by":"crossref","unstructured":"H. Sharma, G. Narang, J. R. Doppa, U. Ogras, P. P. Pande, Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads, in: 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2024, pp. 1\u20136, http:\/\/dx.doi.org\/10.23919\/DATE58400.2024.10546730.","DOI":"10.23919\/DATE58400.2024.10546730"},{"issue":"3","key":"10.1016\/j.future.2026.108565_b17","first-page":"27","article-title":"Prime: a novel processing-in-memory architecture for neural network computation in reram-based main memory","volume":"44","author":"Chi","year":"2016"},{"issue":"7290","key":"10.1016\/j.future.2026.108565_b18","doi-asserted-by":"crossref","first-page":"873","DOI":"10.1038\/nature08940","article-title":"\u2018Memristive\u2019switches enable \u2018stateful\u2019logic operations via material implication","volume":"464","author":"Borghetti","year":"2010","journal-title":"Nature"},{"issue":"5","key":"10.1016\/j.future.2026.108565_b19","doi-asserted-by":"crossref","first-page":"1495","DOI":"10.1109\/TCSI.2020.2965935","article-title":"A memristive multiplier using semi-serial imply-based adder","volume":"67","author":"Radakovits","year":"2020","journal-title":"IEEE Trans. Circuits Syst. I. Regul. Pap."},{"key":"10.1016\/j.future.2026.108565_b20","series-title":"2016 IEEE Computer Society Annual Symposium on VLSI","first-page":"643","article-title":"Memristor-based discrete fourier transform for improving performance and energy efficiency","author":"Cai","year":"2016"},{"issue":"7792","key":"10.1016\/j.future.2026.108565_b21","doi-asserted-by":"crossref","first-page":"641","DOI":"10.1038\/s41586-020-1942-4","article-title":"Fully hardware-implemented memristor convolutional neural network","volume":"577","author":"Yao","year":"2020","journal-title":"Nature"},{"key":"10.1016\/j.future.2026.108565_b22","series-title":"2016 IEEE International Conference on Electro Information Technology","first-page":"0610","article-title":"Fpga-based ultrasonic signal processing platform","author":"Lu","year":"2016"},{"key":"10.1016\/j.future.2026.108565_b23","series-title":"2016 IEEE International Conference on Electro Information Technology","first-page":"0448","article-title":"Ultrasonic signal acquisition and processing platform based on zynq soc","author":"Wang","year":"2016"},{"issue":"3","key":"10.1016\/j.future.2026.108565_b24","doi-asserted-by":"crossref","first-page":"738","DOI":"10.1109\/JSSC.2015.2505714","article-title":"A column-row-parallel asic architecture for 3-d portable medical ultrasonic imaging","volume":"51","author":"Chen","year":"2015","journal-title":"IEEE J. Solid-State Circuits"},{"key":"10.1016\/j.future.2026.108565_b25","doi-asserted-by":"crossref","unstructured":"J. Haase, Parametrization of resistive crossbar arrays for vector matrix multiplication, in: Proceedings of the 9th International Workshop on Equation-Based Object-Oriented Modeling Languages and Tools, 2019, pp. 37\u201344.","DOI":"10.1145\/3365984.3365987"},{"issue":"4","key":"10.1016\/j.future.2026.108565_b26","doi-asserted-by":"crossref","first-page":"65","DOI":"10.1145\/1498765.1498785","article-title":"Roofline: An insightful visual performance model for multicore architectures","volume":"52","author":"Williams","year":"2009","journal-title":"Commun. ACM"},{"issue":"8","key":"10.1016\/j.future.2026.108565_b27","first-page":"786","article-title":"VTEAM\u2014a general model for voltage-controlled memristors","volume":"62","author":"Kvatinsky","year":"2015","journal-title":"IEEE Trans. Circuits Syst. II, Exp. Briefs"},{"key":"10.1016\/j.future.2026.108565_b28","series-title":"2016 IEEE International Solid-State Circuits Conference","first-page":"460","article-title":"27.3 Area-efficient 1gs\/s 6b sar adc with charge-injection-cell-based dac","author":"Choo","year":"2016"},{"key":"10.1016\/j.future.2026.108565_b29","series-title":"Cyclone III Device Handbook","author":"(now Intel)","year":"2012"},{"key":"10.1016\/j.future.2026.108565_b30","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/OJNANO.2024.3494544","article-title":"Portable and cost-effective handheld ultrasound system utilizing FPGA-based synthetic aperture imaging","volume":"5","author":"Wang","year":"2024","journal-title":"IEEE Open J. Nanotechnol."},{"key":"10.1016\/j.future.2026.108565_b31","series-title":"Zynq UltraScale+ MPSoC data sheet: Overview (DS891), xCZU7EV: 504K system logic cells, block RAM 11Mbit, UltraRAM, 16 nm FinFET+","author":"AMD (Xilinx)","year":"2024"},{"key":"10.1016\/j.future.2026.108565_b32","series-title":"Jetson xavier NX module data sheet, 384 CUDA cores, 48 tensor cores, 8 GB LPDDR4x, 10\u201315 W TDP, 12 nm","author":"NVIDIA Corporation","year":"2020"},{"issue":"27","key":"10.1016\/j.future.2026.108565_b33","doi-asserted-by":"crossref","DOI":"10.1073\/pnas.2019339118","article-title":"Ultrasound-on-chip platform for medical imaging, analysis, and collective intelligence","volume":"118","author":"Rothberg","year":"2021","journal-title":"Proc. Natl. Acad. Sci. USA"}],"container-title":["Future Generation Computer Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167739X26001998?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167739X26001998?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,7,4]],"date-time":"2026-07-04T01:04:19Z","timestamp":1783127059000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0167739X26001998"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,10]]},"references-count":33,"alternative-id":["S0167739X26001998"],"URL":"https:\/\/doi.org\/10.1016\/j.future.2026.108565","relation":{},"ISSN":["0167-739X"],"issn-type":[{"value":"0167-739X","type":"print"}],"subject":[],"published":{"date-parts":[[2026,10]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Unified processing-in-memory for ultrasound imaging: A dual-kernel memristor architecture with pipeline-aware scheduling","name":"articletitle","label":"Article Title"},{"value":"Future Generation Computer Systems","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.future.2026.108565","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}],"article-number":"108565"}}