{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,15]],"date-time":"2026-05-15T08:13:49Z","timestamp":1778832829593,"version":"3.51.4"},"reference-count":31,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62204150"],"award-info":[{"award-number":["62204150"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100007219","name":"Natural Science Foundation of Shanghai Municipality","doi-asserted-by":"publisher","award":["23ZR1422500"],"award-info":[{"award-number":["23ZR1422500"]}],"id":[{"id":"10.13039\/100007219","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100007219","name":"Natural Science Foundation of Shanghai Municipality","doi-asserted-by":"publisher","award":["JJ-ZDHYLY-01-23-0004"],"award-info":[{"award-number":["JJ-ZDHYLY-01-23-0004"]}],"id":[{"id":"10.13039\/100007219","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microelectronics Journal"],"published-print":{"date-parts":[[2026,7]]},"DOI":"10.1016\/j.mejo.2026.107180","type":"journal-article","created":{"date-parts":[[2026,4,3]],"date-time":"2026-04-03T06:20:55Z","timestamp":1775197255000},"page":"107180","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["A novel design for SRAM bitcell with 3-complementary-FETs"],"prefix":"10.1016","volume":"173","author":[{"given":"Xiaoyu","family":"Cheng","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yangyang","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tianci","family":"Miao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenbo","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qihang","family":"Zheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kaiyuan","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yisi","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie","family":"Liang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liang","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aiying","family":"Guo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luqiao","family":"Yin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jianhua","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4000-3030","authenticated-orcid":false,"given":"Kailin","family":"Ren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"issue":"3","key":"10.1016\/j.mejo.2026.107180_bib1","doi-asserted-by":"crossref","first-page":"883","DOI":"10.1109\/TED.2023.3235701","article-title":"CFET SRAM DTCO, interconnect guideline, and benchmark for CMOS scaling","volume":"70","author":"Liu","year":"2023","journal-title":"IEEE Trans. Electron. Dev."},{"issue":"3","key":"10.1016\/j.mejo.2026.107180_bib2","doi-asserted-by":"crossref","first-page":"nwae008","DOI":"10.1093\/nsr\/nwae008","article-title":"New structure transistors for advanced technology node CMOS ICs","volume":"11","author":"Zhang","year":"2024","journal-title":"Natl. Sci. Rev."},{"issue":"6","key":"10.1016\/j.mejo.2026.107180_bib3","doi-asserted-by":"crossref","first-page":"2604","DOI":"10.1109\/TED.2017.2688134","article-title":"Physical insights into the nature of gate-induced drain leakage in ultrashort channel nanowire FETs","volume":"64","author":"Sahay","year":"2017","journal-title":"IEEE Trans. Electron. Dev."},{"key":"10.1016\/j.mejo.2026.107180_bib4","series-title":"Proc. 35th Symp. Microelectron. Technol. Devices (SBMicro), Campinas, Brazil","first-page":"1","article-title":"Influence of the quantum effect on the GAA nanosheet NMOS from 200\u00b0C down to -100\u00b0C","author":"Leal","year":"2021"},{"key":"10.1016\/j.mejo.2026.107180_bib5","series-title":"Proc. IEEE Int. Electron Devices Meet. (IEDM), Baltimore, MD, USA","first-page":"1","article-title":"High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling","author":"Bangsaruntip","year":"2009"},{"key":"10.1016\/j.mejo.2026.107180_bib6","series-title":"Proc. Symp. VLSI Technol., Kyoto, Japan","first-page":"T140","article-title":"Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance","author":"Lauer","year":"2015"},{"key":"10.1016\/j.mejo.2026.107180_bib7","series-title":"Proc. IEEE SOI-3D-Subthreshold Microelectron. Technol. Unified Conf. (S3S), Rohnert Park, CA, USA","first-page":"1","article-title":"Performance trade-offs in FinFET and gate-all-around device architectures for 7nm-node and beyond","author":"Kim","year":"2015"},{"key":"10.1016\/j.mejo.2026.107180_bib8","series-title":"Proc. IEEE Int. Electron Devices Meet. (IEDM), San Francisco, CA, USA","first-page":"19.7.1","article-title":"Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates","author":"Mertens","year":"2016"},{"issue":"12","key":"10.1016\/j.mejo.2026.107180_bib9","doi-asserted-by":"crossref","first-page":"6118","DOI":"10.1109\/TED.2023.3323449","article-title":"Vertically stacked nanosheet number optimization strategy for complementary FET (CFET) scaling beyond 2 nm","volume":"70","author":"Li","year":"2023","journal-title":"IEEE Trans. Electron. Dev."},{"key":"10.1016\/j.mejo.2026.107180_bib10","series-title":"Proc. IEEE Int. Electron Devices Meet. (IEDM), San Francisco, CA, USA","first-page":"1","article-title":"3D stacked devices and MOL innovations for post-nanosheet CMOS scaling","author":"Horiguchi","year":"2023"},{"key":"10.1016\/j.mejo.2026.107180_bib11","series-title":"Proc. IEEE Int. Electron Devices Meet. (IEDM), San Francisco, CA, USA","first-page":"3.1.1","article-title":"CFET design options, challenges, and opportunities for 3D integration","author":"Liebmann","year":"2021"},{"key":"10.1016\/j.mejo.2026.107180_bib12","series-title":"Proc. IEEE Symp. VLSI Technol., Honolulu, HI, USA","first-page":"141","article-title":"The complementary FET (CFET) for CMOS scaling beyond N3","author":"Ryckaert","year":"2018"},{"issue":"12","key":"10.1016\/j.mejo.2026.107180_bib13","doi-asserted-by":"crossref","first-page":"5349","DOI":"10.1109\/TED.2020.3033510","article-title":"Buried power rail integration with FinFETs for ultimate CMOS scaling","volume":"67","author":"Gupta","year":"2020","journal-title":"IEEE Trans. Electron. Dev."},{"key":"10.1016\/j.mejo.2026.107180_bib14","series-title":"Proc. 9th IEEE Electron Devices Technol. Manuf. Conf. (EDTM), Hong Kong, China","first-page":"1","article-title":"Low thermal budget ultrathin Ti silicide for advanced backside contact of backside power delivery network (BSPDN)","author":"Liao","year":"2025"},{"key":"10.1016\/j.mejo.2026.107180_bib15","first-page":"1","article-title":"Area-adjusted comparison of BSPDN interconnects in CFET: superiority of frontside connection","author":"Lee","year":"2025","journal-title":"IEEE Trans. Electron. Dev."},{"key":"10.1016\/j.mejo.2026.107180_bib16","series-title":"Proc. IEEE Int. Electron Devices Meet. (IEDM), San Francisco, CA, USA","first-page":"1","article-title":"Backside power delivery: game changer and key enabler of advanced logic scaling and new STCO opportunities","author":"Veloso","year":"2023"},{"key":"10.1016\/j.mejo.2026.107180_bib17","series-title":"Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan","first-page":"1","article-title":"PPA and scaling potential of backside power options in N2 and A14 nanosheet technology","author":"Yang","year":"2023"},{"key":"10.1016\/j.mejo.2026.107180_bib18","series-title":"Proc. China Semicond. Technol. Int. Conf. (CSTIC), Shanghai, China","first-page":"1","article-title":"CFET 6T HD SRAM designs with 3nm design rule","author":"Zhu","year":"2022"},{"key":"10.1016\/j.mejo.2026.107180_bib19","series-title":"Proc. IEEE Symp. VLSI Technol., Honolulu, HI, USA","first-page":"1","article-title":"First monolithic integration of 3D complementary FET (CFET) on 300mm wafers","author":"Subramanian","year":"2020"},{"key":"10.1016\/j.mejo.2026.107180_bib20","series-title":"Proc. IEEE Int. Electron Devices Meet. (IEDM), San Francisco, CA, USA","first-page":"20.6.1","article-title":"3-D self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued Moore's law scaling","author":"Huang","year":"2020"},{"key":"10.1016\/j.mejo.2026.107180_bib21","series-title":"Proc. IEEE Int. Electron Devices Meet. (IEDM), San Francisco, CA, USA","first-page":"11.7.1","article-title":"First demonstration of CMOS inverter and 6T-SRAM based on GAA CFETs structure for 3D-IC applications","author":"Chang","year":"2019"},{"key":"10.1016\/j.mejo.2026.107180_bib22","series-title":"Proc. Int. Symp. VLSI Technol., Syst. Appl. (VLSI-TSA), Hsinchu, Taiwan","first-page":"1","article-title":"Junctionless gate-all-around pFETs on Si with in-situ doped Ge channel","author":"Wong","year":"2015"},{"key":"10.1016\/j.mejo.2026.107180_bib23","series-title":"Proc. Symp. VLSI Technol., Kyoto, Japan","first-page":"T230","article-title":"Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET","author":"Loubet","year":"2017"},{"issue":"12","key":"10.1016\/j.mejo.2026.107180_bib24","doi-asserted-by":"crossref","first-page":"6106","DOI":"10.1109\/TED.2021.3121349","article-title":"The complementary FET (CFET) 6T-SRAM","volume":"68","author":"Gupta","year":"2021","journal-title":"IEEE Trans. Electron. Dev."},{"key":"10.1016\/j.mejo.2026.107180_bib25","series-title":"Proc. IEEE Int. Electron Devices Meet. (IEDM), San Francisco, CA, USA","first-page":"22.5.1","article-title":"Buried power rail metal exploration towards the 1 nm node","author":"Gupta","year":"2021"},{"issue":"5","key":"10.1016\/j.mejo.2026.107180_bib26","doi-asserted-by":"crossref","first-page":"748","DOI":"10.1109\/JSSC.1987.1052809","article-title":"Static-noise margin analysis of MOS SRAM cells","volume":"22","author":"Seevinck","year":"1987","journal-title":"IEEE J. Solid State Circ."},{"key":"10.1016\/j.mejo.2026.107180_bib27","doi-asserted-by":"crossref","first-page":"166222","DOI":"10.1109\/ACCESS.2025.3611787","article-title":"A CNTFET-based 10T static memory design immune to read and half-select disturbs for low-power wearable biomedical systems","volume":"13","author":"Ul Haq","year":"2025","journal-title":"IEEE Access"},{"key":"10.1016\/j.mejo.2026.107180_bib28","doi-asserted-by":"crossref","DOI":"10.1016\/j.aeue.2025.155884","article-title":"A stable, low-power SRAM cell with half-select immunity in CNTFET technology","volume":"199","author":"Haq","year":"2025","journal-title":"AE\u00dc, Int. J. Electron. Commun."},{"key":"10.1016\/j.mejo.2026.107180_bib29","series-title":"Proc. Int. Symp. Low Power Electron. Des. (ISLPED), Bangalore, India","first-page":"129","article-title":"Analyzing static and dynamic write margin for nanometer SRAMs","author":"Wang","year":"2008"},{"issue":"5","key":"10.1016\/j.mejo.2026.107180_bib30","doi-asserted-by":"crossref","first-page":"1433","DOI":"10.1109\/JSSC.1989.572629","article-title":"Matching properties of MOS transistors","volume":"24","author":"Pelgrom","year":"1989","journal-title":"IEEE J. Solid State Circ."},{"key":"10.1016\/j.mejo.2026.107180_bib31","series-title":"Proc. Symp. VLSI Technol., Kyoto, Japan","first-page":"86","article-title":"Simulation of statistical variability in nano MOSFETs","author":"Asenov","year":"2007"}],"container-title":["Microelectronics Journal"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126001360?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126001360?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,5,15]],"date-time":"2026-05-15T08:01:39Z","timestamp":1778832099000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1879239126001360"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,7]]},"references-count":31,"alternative-id":["S1879239126001360"],"URL":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107180","relation":{},"ISSN":["1879-2391"],"issn-type":[{"value":"1879-2391","type":"print"}],"subject":[],"published":{"date-parts":[[2026,7]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A novel design for SRAM bitcell with 3-complementary-FETs","name":"articletitle","label":"Article Title"},{"value":"Microelectronics Journal","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107180","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Elsevier Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}],"article-number":"107180"}}