{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,15]],"date-time":"2026-05-15T08:15:02Z","timestamp":1778832902963,"version":"3.51.4"},"reference-count":25,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microelectronics Journal"],"published-print":{"date-parts":[[2026,7]]},"DOI":"10.1016\/j.mejo.2026.107186","type":"journal-article","created":{"date-parts":[[2026,3,23]],"date-time":"2026-03-23T16:37:37Z","timestamp":1774283857000},"page":"107186","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["PASO: A PVT-Aware device Sizing framework for OTA circuit with sub-block annotation-based parameter reduction"],"prefix":"10.1016","volume":"173","author":[{"given":"Jinglin","family":"Han","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yanxi","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haoyu","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yue","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2006-408X","authenticated-orcid":false,"given":"Peng","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/j.mejo.2026.107186_b1","series-title":"2025 Design, Automation & Test in Europe Conference (DATE)","first-page":"1","article-title":"Accelerating ota circuit design: Transistor sizing based on a transformer model and precomputed lookup tables","author":"Ghosh","year":"2025"},{"key":"10.1016\/j.mejo.2026.107186_b2","series-title":"International Conference on Machine Learning","first-page":"38485","article-title":"Constrained efficient global optimization of expensive black-box functions","author":"Xu","year":"2023"},{"issue":"1","key":"10.1016\/j.mejo.2026.107186_b3","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TCAD.2021.3054811","article-title":"An efficient batch-constrained bayesian optimization approach for analog circuit synthesis via multiobjective acquisition ensemble","volume":"41","author":"Zhang","year":"2021","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"10.1016\/j.mejo.2026.107186_b4","doi-asserted-by":"crossref","unstructured":"T. Gu, R. Lyu, Z. Bi, C. Yan, F. Yang, D. Zhou, T. Cui, X. Liu, Z. Zhang, X. Zeng, Himoss: A novel high-dimensional multi-objective optimization method via adaptive gradient-based subspace sampling for analog circuit sizing, in: Proceedings of the 61st ACM\/IEEE Design Automation Conference, 2024, pp. 1\u20136.","DOI":"10.1145\/3649329.3657318"},{"key":"10.1016\/j.mejo.2026.107186_b5","article-title":"Rose-opt: Robust and efficient analog circuit parameter optimization with knowledge-infused reinforcement learning","author":"Cao","year":"2024","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"10.1016\/j.mejo.2026.107186_b6","series-title":"2025 ACM\/IEEE 7th Symposium on Machine Learning for CAD","first-page":"1","article-title":"Hr 2: A pvt aware hierarchical rl based sizing framework for robust analog circuit design","author":"Jung","year":"2025"},{"key":"10.1016\/j.mejo.2026.107186_b7","doi-asserted-by":"crossref","unstructured":"W. Shi, H. Wang, J. Gu, M. Liu, D.Z. Pan, S. Han, N. Sun, Robustanalog: Fast variation-aware analog circuit design via multi-task rl, in: Proceedings of the 2022 ACM\/IEEE Workshop on Machine Learning for CAD, 2022, pp. 35\u201341.","DOI":"10.1145\/3551901.3556487"},{"key":"10.1016\/j.mejo.2026.107186_b8","doi-asserted-by":"crossref","unstructured":"Z. Kong, X. Tang, W. Shi, Y. Du, Y. Lin, Y. Wang, Pvtsizing: A turbo-rl-based batch-sampling optimization framework for pvt-robust analog circuit synthesis, in: Proceedings of the 61st ACM\/IEEE Design Automation Conference, 2024, pp. 1\u20136.","DOI":"10.1145\/3649329.3661850"},{"key":"10.1016\/j.mejo.2026.107186_b9","doi-asserted-by":"crossref","first-page":"70353","DOI":"10.1109\/ACCESS.2021.3078240","article-title":"In-depth design space exploration of 26.5-to-29.5-ghz 65-nm cmos low-noise amplifiers for low-footprint-and-power 5 g communications using one-and-two-step design optimization","volume":"9","author":"Mendes","year":"2021","journal-title":"IEEE Access"},{"issue":"5","key":"10.1016\/j.mejo.2026.107186_b10","doi-asserted-by":"crossref","first-page":"2017","DOI":"10.1109\/TCSI.2023.3340683","article-title":"Knowledge transfer framework for pvt robustness in analog integrated circuits","volume":"71","author":"Li","year":"2023","journal-title":"IEEE Trans. Circuits Syst. I. Regul. Pap."},{"key":"10.1016\/j.mejo.2026.107186_b11","doi-asserted-by":"crossref","DOI":"10.1016\/j.aei.2025.104195","article-title":"Multitask evolution with problem reformulation for global exploration in analog circuit design","volume":"70","author":"Li","year":"2026","journal-title":"Adv. Eng. Inform."},{"key":"10.1016\/j.mejo.2026.107186_b12","article-title":"Scalable global optimization via local bayesian optimization","volume":"32","author":"Eriksson","year":"2019","journal-title":"Adv. Neural Inf. Process. Syst."},{"key":"10.1016\/j.mejo.2026.107186_b13","series-title":"2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)","first-page":"1","article-title":"Tss-bo: Scalable bayesian optimization for analog circuit sizing via truncated subspace sampling","author":"Gu","year":"2024"},{"key":"10.1016\/j.mejo.2026.107186_b14","series-title":"2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design","first-page":"1","article-title":"A novel simulations scheduler for automated circuit sizing algorithms","author":"Vi\u015fan","year":"2024"},{"key":"10.1016\/j.mejo.2026.107186_b15","series-title":"2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design","first-page":"1","article-title":"A comparative study on the incorporation of pvt corner conditions within reinforcement learning-based analog ic sizing approaches","author":"Costa","year":"2025"},{"key":"10.1016\/j.mejo.2026.107186_b16","series-title":"2022 IEEE International Symposium on Circuits and Systems","first-page":"1570","article-title":"Speeding-up complex rf ic sizing optimizations with a process, voltage and temperature corner performance estimator based on anns","author":"Vaz","year":"2022"},{"key":"10.1016\/j.mejo.2026.107186_b17","doi-asserted-by":"crossref","DOI":"10.1016\/j.eswa.2025.126966","article-title":"Hierarchical multi-task circuit modeling for pvt robustness via kan-cnn integration","volume":"274","author":"Cai","year":"2025","journal-title":"Expert Syst. Appl."},{"key":"10.1016\/j.mejo.2026.107186_b18","series-title":"2020 57th ACM\/IEEE Design Automation Conference","first-page":"1","article-title":"ParaGraph: Layout parasitics and device parameter prediction using graph neural networks","author":"Ren","year":"2020"},{"issue":"10","key":"10.1016\/j.mejo.2026.107186_b19","doi-asserted-by":"crossref","first-page":"1367","DOI":"10.1109\/TPAMI.2004.75","article-title":"A (sub)graph isomorphism algorithm for matching large graphs","volume":"26","author":"Cordella","year":"2004","journal-title":"IEEE Trans. Pattern Anal. Mach. Intell."},{"issue":"9","key":"10.1016\/j.mejo.2026.107186_b20","first-page":"2539","article-title":"Weisfeiler-lehman graph kernels","volume":"12","author":"Shervashidze","year":"2011","journal-title":"J. Mach. Learn. Res."},{"key":"10.1016\/j.mejo.2026.107186_b21","series-title":"Uncertainty in Artificial Intelligence","first-page":"507","article-title":"Multi-objective bayesian optimization over high-dimensional search spaces","author":"Daulton","year":"2022"},{"key":"10.1016\/j.mejo.2026.107186_b22","series-title":"International Conference on Artificial Intelligence and Statistics","first-page":"730","article-title":"Scalable constrained bayesian optimization","author":"Eriksson","year":"2021"},{"key":"10.1016\/j.mejo.2026.107186_b23","series-title":"2025 China postgraduate ic innovation competition, eda elite challenge contest","year":"2025"},{"key":"10.1016\/j.mejo.2026.107186_b24","doi-asserted-by":"crossref","unstructured":"J. Han, Y. Leng, X. Zhang, P. Wang, Tso-flow: A topology synthesis and optimization workflow for operational amplifiers with invertible graph generative model, in: Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design, 2024, pp. 1\u20139.","DOI":"10.1145\/3676536.3676693"},{"issue":"1","key":"10.1016\/j.mejo.2026.107186_b25","first-page":"199","article-title":"Area optimisation of two stage miller compensated op-amp in 65 nm using hybrid pso","volume":"69","author":"Rashid","year":"2021","journal-title":"IEEE Trans. Circuits Syst. II: Express Briefs"}],"container-title":["Microelectronics Journal"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126001426?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126001426?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,5,15]],"date-time":"2026-05-15T08:03:23Z","timestamp":1778832203000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1879239126001426"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,7]]},"references-count":25,"alternative-id":["S1879239126001426"],"URL":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107186","relation":{},"ISSN":["1879-2391"],"issn-type":[{"value":"1879-2391","type":"print"}],"subject":[],"published":{"date-parts":[[2026,7]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"PASO: A PVT-Aware device Sizing framework for OTA circuit with sub-block annotation-based parameter reduction","name":"articletitle","label":"Article Title"},{"value":"Microelectronics Journal","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107186","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Elsevier Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}],"article-number":"107186"}}