{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T04:54:08Z","timestamp":1781585648479,"version":"3.54.5"},"reference-count":36,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T00:00:00Z","timestamp":1785542400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T00:00:00Z","timestamp":1785542400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T00:00:00Z","timestamp":1785542400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T00:00:00Z","timestamp":1785542400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T00:00:00Z","timestamp":1785542400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T00:00:00Z","timestamp":1785542400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T00:00:00Z","timestamp":1785542400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microelectronics Journal"],"published-print":{"date-parts":[[2026,8]]},"DOI":"10.1016\/j.mejo.2026.107268","type":"journal-article","created":{"date-parts":[[2026,5,14]],"date-time":"2026-05-14T12:23:53Z","timestamp":1778761433000},"page":"107268","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["ALCAR: Adaptive load-balanced congestion-aware routing algorithm for dual-layer networks-on-chip"],"prefix":"10.1016","volume":"174","author":[{"given":"Xiaofeng","family":"Zou","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yuanxi","family":"Peng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yongzheng","family":"Zhan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Lu","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"78","reference":[{"key":"10.1016\/j.mejo.2026.107268_bib1","doi-asserted-by":"crossref","first-page":"185992","DOI":"10.1109\/ACCESS.2020.3030606","article-title":"Noc2: an efficient interfacing approach for heavily-communicating noc-based systems","volume":"8","author":"Morgan","year":"2020","journal-title":"IEEE Access"},{"key":"10.1016\/j.mejo.2026.107268_bib2","article-title":"A tree-recursive partitioned multicast mechanism for noc-based deep neural network accelerator","volume":"147","author":"Ouyang","year":"2024","journal-title":"Microelectron. J."},{"issue":"9","key":"10.1016\/j.mejo.2026.107268_bib3","doi-asserted-by":"crossref","first-page":"1283","DOI":"10.1109\/TC.2019.2906869","article-title":"Cdxbar: a converge-diverge crossbar network for high-performance gpus","volume":"68","author":"Zhao","year":"2019","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/j.mejo.2026.107268_bib4","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/OJCAS.2024.3518110","article-title":"Pasithea-1: an energy-efficient sequential reconfigurable array with cpu-like programmability","volume":"6","author":"Kaiser","year":"2025","journal-title":"IEEE Open Journal of Circuits and Systems"},{"issue":"5","key":"10.1016\/j.mejo.2026.107268_bib5","doi-asserted-by":"crossref","first-page":"1316","DOI":"10.1109\/TCAD.2021.3091961","article-title":"Arsmart: an improved smart noc design supporting arbitrary-turn transmission","volume":"41","author":"Chen","year":"2022","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"key":"10.1016\/j.mejo.2026.107268_bib6","series-title":"2024 International Conference on Engineering Computing Technologies (ICECT)","first-page":"1","article-title":"A review of optimization techniques in network-on-chip (noc) architecture","author":"Khan","year":"2024"},{"key":"10.1016\/j.mejo.2026.107268_bib7","series-title":"2024 17th IEEE\/ACM International Workshop on Network on Chip Architectures (NoCArc)","first-page":"1","article-title":"Latest innovations in intelligent network-on-chip architectures: a systematic review","author":"Kakoulli","year":"2024"},{"key":"10.1016\/j.mejo.2026.107268_bib8","article-title":"\u201cPRLM: a parallel loading mechanism for a deep neural network accelerator based on noc","volume":"160","author":"Ouyang","year":"2025","journal-title":"Microelectron. J."},{"key":"10.1016\/j.mejo.2026.107268_bib9","series-title":"2022 4th International Conference on Advances in Computer Technology, Information Science and Communications (CTISC)","first-page":"1","article-title":"Efficient load balance algorithm for network-on-chip mapping","author":"He","year":"2022"},{"issue":"12","key":"10.1016\/j.mejo.2026.107268_bib10","doi-asserted-by":"crossref","first-page":"5232","DOI":"10.1109\/TCAD.2022.3151021","article-title":"LAMP: Load-balanced multipath parallel transmission in point-to-point nocs","volume":"41","author":"Chen","year":"2022","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"key":"10.1016\/j.mejo.2026.107268_bib11","article-title":"Design of a highperformance router with distributed shared-buffer for load balancing for on-chip networks","volume":"132","author":"Rezaei-Zare","year":"2023","journal-title":"Microelectron. J."},{"issue":"2","key":"10.1016\/j.mejo.2026.107268_bib12","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1109\/LES.2021.3113355","article-title":"Arc model and ddg: deadlock avoidance and detection in torus noc","volume":"14","author":"Das","year":"2022","journal-title":"IEEE Embedded Sys. Lett."},{"key":"10.1016\/j.mejo.2026.107268_bib13","series-title":"2015 Seventh International Symposium on Parallel Architectures, Algorithms and Programming (PAAP)","first-page":"122","article-title":"Two modified multicast algorithms for two dimensional mesh and torus networks","author":"Harutyunyan","year":"2015"},{"issue":"10","key":"10.1016\/j.mejo.2026.107268_bib14","doi-asserted-by":"crossref","first-page":"1095","DOI":"10.1007\/s11227-025-07580-5","article-title":"Adaptive multi-beltway thermal-aware routing algorithm for 3d noc system","volume":"81","author":"Dadmand","year":"2025","journal-title":"J. Supercomput."},{"key":"10.1016\/j.mejo.2026.107268_bib15","doi-asserted-by":"crossref","first-page":"126679","DOI":"10.1109\/ACCESS.2024.3425900","article-title":"BTSAM: balanced thermal-state-aware mapping algorithms and architecture for 3d-noc-based neuromorphic systems","volume":"12","author":"Maatar","year":"2024","journal-title":"IEEE Access"},{"key":"10.1016\/j.mejo.2026.107268_bib16","doi-asserted-by":"crossref","first-page":"199","DOI":"10.1016\/j.jpdc.2022.04.019","article-title":"Understanding node connection modes in multi-rail fat-tree","volume":"167","author":"Wang","year":"2022","journal-title":"J. Parallel Distr. Comput."},{"key":"10.1016\/j.mejo.2026.107268_bib17","series-title":"2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)","first-page":"154","article-title":"Enhancing butterfly fat tree nocs for FPGAs with lightweight flow control","author":"Malik","year":"2019"},{"key":"10.1016\/j.mejo.2026.107268_bib18","series-title":"2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA)","first-page":"957","article-title":"Stay in your Lane: a noc with low-overhead multipacket bypassing","author":"Farrokhbakht","year":"2022"},{"key":"10.1016\/j.mejo.2026.107268_bib19","doi-asserted-by":"crossref","DOI":"10.1016\/j.compeleceng.2022.108404","article-title":"Performance evaluation of modified mesh-based noc architecture","volume":"104","author":"Naresh Kumar Reddy","year":"2022","journal-title":"Comput. Electr. Eng."},{"key":"10.1016\/j.mejo.2026.107268_bib20","series-title":"2017 International Conference on Engineering MIS (ICEMIS)","first-page":"1","article-title":"Architecture and performances comparison of network on chip router for hierarchical mesh topology","author":"Chemli","year":"2017"},{"key":"10.1016\/j.mejo.2026.107268_bib21","series-title":"2022 IEEE 19 India Council International Conference (INDICON)","first-page":"1","article-title":"An efficient low-power vip-based vc router architecture for mesh-based noc","author":"Reddy","year":"2022"},{"issue":"2","key":"10.1016\/j.mejo.2026.107268_bib22","doi-asserted-by":"crossref","first-page":"295","DOI":"10.1109\/TC.2011.237","article-title":"Elastic buffer flow control for on-chip networks","volume":"62","author":"Michelogiannakis","year":"2013","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/j.mejo.2026.107268_bib23","series-title":"2024 Great Lakes Symposium on VLSI","first-page":"364","article-title":"Ttnnm: thermaland traffic-aware neural network mapping on 3d-noc-based accelerator","author":"Li","year":"2024"},{"key":"10.1016\/j.mejo.2026.107268_bib24","series-title":"2024 34th International Conference on Field-Programmable Logic and Applications (FPL)","first-page":"33","article-title":"The road less traveled: Congestion-aware noc placement and packet routing for fpgas","author":"Shahrouz","year":"2024"},{"issue":"5","key":"10.1016\/j.mejo.2026.107268_bib25","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1145\/165660.165667","article-title":"Improved parallel i\/o via a two-phase run-time access strategy","volume":"21","author":"Del Rosario","year":"1993","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"10.1016\/j.mejo.2026.107268_bib26","series-title":"32nd International Symposium on Computer Architecture (ISCA)","first-page":"432","article-title":"Near-optimal worst-case throughput routing for two-dimensional mesh networks","author":"Seo","year":"2005"},{"key":"10.1016\/j.mejo.2026.107268_bib27","series-title":"2011 38th Annual International Symposium on Computer Architecture (ISCA)","first-page":"389","article-title":"A case for heterogeneous on-chip interconnects for cmps","author":"Mishra","year":"2011"},{"key":"10.1016\/j.mejo.2026.107268_bib28","series-title":"2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS)","first-page":"86","article-title":"A detailed and flexible cycle-accurate network-on-chip simulator","author":"Jiang","year":"2013"},{"key":"10.1016\/j.mejo.2026.107268_bib29","article-title":"An efficient adaptive routing algorithm for the co-optimization of fault tolerance and congestion awareness based on 3d noc","volume":"142","author":"Li","year":"2023","journal-title":"Microelectron. J."},{"issue":"4","key":"10.1016\/j.mejo.2026.107268_bib30","doi-asserted-by":"crossref","first-page":"203","DOI":"10.1109\/LES.2022.3176233","article-title":"A q-learning-based faulttolerant and congestion-aware adaptive routing algorithm for networks-on-chip","volume":"14","author":"Liu","year":"2022","journal-title":"IEEE Embedded Sys. Lett."},{"issue":"5","key":"10.1016\/j.mejo.2026.107268_bib31","first-page":"367","article-title":"Parametric evaluation of routing algorithms in network on chip architecture","volume":"35","author":"Nejad","year":"2020","journal-title":"Microelectron. J."},{"issue":"10","key":"10.1016\/j.mejo.2026.107268_bib32","doi-asserted-by":"crossref","first-page":"1725","DOI":"10.1109\/TCAD.2017.2648817","article-title":"LAXY: a location-based aging-resilient xy-yx routing algorithm for network on chip","volume":"36","author":"Rohbani","year":"2017","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"issue":"10","key":"10.1016\/j.mejo.2026.107268_bib33","doi-asserted-by":"crossref","first-page":"1081","DOI":"10.1109\/TVLSI.2007.893649","article-title":"3D topologies for networks-on-chip","volume":"15","author":"Pavlidis","year":"2007","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"1","key":"10.1016\/j.mejo.2026.107268_bib34","doi-asserted-by":"crossref","DOI":"10.1002\/dac.5360","article-title":"Low-cost regional-based congestion-aware routing algorithm for 2d mesh noc","volume":"36","author":"Vazifedunn","year":"2023","journal-title":"Int. J. Commun. Syst."},{"issue":"8","key":"10.1016\/j.mejo.2026.107268_bib35","doi-asserted-by":"crossref","first-page":"2278","DOI":"10.1109\/TC.2023.3248260","article-title":"Adele+: an adaptive congestionand-energy-aware elevator selection for partially connected 3d networkson-chip","volume":"72","author":"Taheri","year":"2023","journal-title":"IEEE Trans. Comput."},{"issue":"15","key":"10.1016\/j.mejo.2026.107268_bib36","doi-asserted-by":"crossref","first-page":"1429","DOI":"10.1007\/s11227-025-07918-z","article-title":"CA-DDP: congestion-aware dynamic dimension prioritization for power-efficient routing algorithm in 3d network-on-chip","volume":"81","author":"Li","year":"2025","journal-title":"J. Supercomput."}],"container-title":["Microelectronics Journal"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126002249?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126002249?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T04:17:06Z","timestamp":1781583426000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1879239126002249"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,8]]},"references-count":36,"alternative-id":["S1879239126002249"],"URL":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107268","relation":{},"ISSN":["1879-2391"],"issn-type":[{"value":"1879-2391","type":"print"}],"subject":[],"published":{"date-parts":[[2026,8]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"ALCAR: Adaptive load-balanced congestion-aware routing algorithm for dual-layer networks-on-chip","name":"articletitle","label":"Article Title"},{"value":"Microelectronics Journal","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107268","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Elsevier Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}],"article-number":"107268"}}