{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T14:19:07Z","timestamp":1783606747066,"version":"3.55.0"},"reference-count":20,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"funder":[{"DOI":"10.13039\/501100006579","name":"Ministry of Industry and Information Technology of the People's Republic of China","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100006579","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microelectronics Journal"],"published-print":{"date-parts":[[2026,9]]},"DOI":"10.1016\/j.mejo.2026.107282","type":"journal-article","created":{"date-parts":[[2026,5,30]],"date-time":"2026-05-30T06:37:44Z","timestamp":1780123064000},"page":"107282","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["A digitally programmable 2.4-GHz background-calibrated fractional output divider with \u221280dBc spur suppression"],"prefix":"10.1016","volume":"175","author":[{"given":"Bo","family":"Cheng","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiangtao","family":"Xu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Huanhuan","family":"Qi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yong","family":"Dai","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hui","family":"Cao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jia","family":"Shen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hong","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"78","reference":[{"issue":"15","key":"10.1016\/j.mejo.2026.107282_bib1","doi-asserted-by":"crossref","first-page":"2347","DOI":"10.3390\/electronics11152347","article-title":"A 500 kHz to 150 MHz multi-output clock generator using analog PLL and open-loop fractional divider with 0.13 \u03bcm CMOS","volume":"11","author":"Jin","year":"2022","journal-title":"Electronics"},{"issue":"3","key":"10.1016\/j.mejo.2026.107282_bib2","first-page":"543","article-title":"A Fractional-N PLL for multiband (0.8\u20136 GHz) communications using binary-weighted D\/A differentiator and offset-frequency delta-sigma modulator","volume":"45","author":"Jian","year":"2010","journal-title":"IEEE J. Solid State Circ."},{"issue":"11","key":"10.1016\/j.mejo.2026.107282_bib3","doi-asserted-by":"crossref","first-page":"1849","DOI":"10.1109\/TCOM.1980.1094619","article-title":"Charge-pump phase-lock loops","volume":"28","author":"Gardner","year":"1980","journal-title":"IEEE Trans. Commun."},{"key":"10.1016\/j.mejo.2026.107282_bib4","series-title":"2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA","article-title":"29.5 A 0.008mm2 1.5mW 0.625-to-200MHz fractional output divider with 120fsrms jitter based on Replica-DTC-Free background calibration","author":"Lin","year":"2021"},{"key":"10.1016\/j.mejo.2026.107282_bib18","article-title":"A DTC-based fractional-N ADPLL using dual-core noise circulating DCO and loop bandwidth control techniques","volume":"156","author":"Xu","year":"2024","journal-title":"Microelectron. J."},{"key":"10.1016\/j.mejo.2026.107282_bib19","doi-asserted-by":"crossref","DOI":"10.1016\/j.mejo.2024.106140","article-title":"A low-noise, 0.05\u201317.8-GHz fractional-N phase-locked loop with two parallel synchronized dual-core voltage-controlled oscillators","volume":"146","author":"Sun","year":"2024","journal-title":"Microelectron. J."},{"key":"10.1016\/j.mejo.2026.107282_bib20","doi-asserted-by":"crossref","DOI":"10.1016\/j.mejo.2023.105753","article-title":"A DTC-based Fractional-N DPLL using probability-density-shaping spur immunity and Q-noise reduction techniques for IoT applications","volume":"135","author":"Jin","year":"2023","journal-title":"Microelectron. J."},{"issue":"10","key":"10.1016\/j.mejo.2026.107282_bib12","doi-asserted-by":"crossref","first-page":"3417","DOI":"10.1109\/JSSC.2024.3396799","article-title":"Design and analysis of a fractional frequency synthesizer with <90-fs jitter and <\u2212103-dBc spurious tones using digital spur cancellation","volume":"59","author":"Zeinali","year":"2024","journal-title":"IEEE J. Solid State Circ."},{"issue":"6","key":"10.1016\/j.mejo.2026.107282_bib5","doi-asserted-by":"crossref","first-page":"1639","DOI":"10.1109\/TCSI.2008.916571","article-title":"A spur elimination technique for phase interpolation-based fractional-N PLLs","volume":"55","author":"Pamarti","year":"2008","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"10.1016\/j.mejo.2026.107282_bib14","series-title":"2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA","first-page":"1","article-title":"A 0.024mm2 all-digital fractional output divider with 257fs worst-case jitter using Split-DTC-Based background calibration","author":"Yu","year":"2025"},{"issue":"6","key":"10.1016\/j.mejo.2026.107282_bib6","doi-asserted-by":"crossref","first-page":"1806","DOI":"10.1109\/JSSC.2018.2817602","article-title":"Low-jitter multi-output all-digital clock generator using DTC-based open-loop fractional dividers","volume":"53","author":"Elkholy","year":"2018","journal-title":"IEEE J. Solid State Circ."},{"issue":"12","key":"10.1016\/j.mejo.2026.107282_bib8","doi-asserted-by":"crossref","first-page":"3184","DOI":"10.1109\/JSSC.2012.2216671","article-title":"A 2.4-GHz 20\u201340-MHz channel WLAN digital outphasing transmitter utilizing a delay-based wideband phase modulator in 32-nm CMOS","volume":"47","author":"Ravi","year":"2012","journal-title":"IEEE J. Solid State Circ."},{"key":"10.1016\/j.mejo.2026.107282_bib9","series-title":"Proc. IEEE Asia Pacific Conf. Circuits Syst.","first-page":"1019","article-title":"A 0.5 V 6-bit scalable phase interpolator","author":"Kumaki","year":"2010"},{"issue":"6","key":"10.1016\/j.mejo.2026.107282_bib10","doi-asserted-by":"crossref","first-page":"1412","DOI":"10.1109\/JSSC.2015.2414421","article-title":"A high-linearity digital-to-time converter technique: constant-slope charging","volume":"50","author":"Ru","year":"2015","journal-title":"IEEE J. Solid State Circ."},{"issue":"3","key":"10.1016\/j.mejo.2026.107282_bib11","doi-asserted-by":"crossref","first-page":"698","DOI":"10.1109\/JSSC.2022.3143468","article-title":"A 3.2-GHz 405 fsrms Jitter \u2013237.2 dB FoMJIT ring-based Fractional-N synthesizer","volume":"57","author":"Elmallah","year":"2022","journal-title":"IEEE J. Solid State Circ."},{"key":"10.1016\/j.mejo.2026.107282_bib13","article-title":"Web-customizable, any-frequency, any-output quad clock generator\/buffer","year":"2021","journal-title":"Si5335 Data Sheet, Rev. 1.4"},{"key":"10.1016\/j.mejo.2026.107282_bib15","series-title":"Design of Integrated Circuits for Optical Communications","first-page":"255","author":"Razavi","year":"2012"},{"issue":"2","key":"10.1016\/j.mejo.2026.107282_bib16","doi-asserted-by":"crossref","first-page":"1031","DOI":"10.26599\/TST.2024.9010162","article-title":"A low-cost open-loop fractional output divider for audio system-on-chip in 180 nm CMOS","volume":"31","author":"Zeng","year":"2026","journal-title":"Tsinghua Sci. Technol."},{"key":"10.1016\/j.mejo.2026.107282_bib17","doi-asserted-by":"crossref","unstructured":"D. Luo et al., \"A compact low-jitter all-digital fractional output divider using Split-DTC-Based background calibration,\" in IEEE J. Solid State Circ., doi: 10.1109\/JSSC.2025.3602127.","DOI":"10.1109\/JSSC.2025.3602127"},{"issue":"1","key":"10.1016\/j.mejo.2026.107282_bib7","first-page":"114","article-title":"Open-loop fractional division using a voltage-comparator-based digital-to-time converter","volume":"63","author":"Swilam","year":"2016","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"}],"container-title":["Microelectronics Journal"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126002389?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126002389?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T13:41:35Z","timestamp":1783604495000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1879239126002389"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,9]]},"references-count":20,"alternative-id":["S1879239126002389"],"URL":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107282","relation":{},"ISSN":["1879-2391"],"issn-type":[{"value":"1879-2391","type":"print"}],"subject":[],"published":{"date-parts":[[2026,9]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A digitally programmable 2.4-GHz background-calibrated fractional output divider with \u221280dBc spur suppression","name":"articletitle","label":"Article Title"},{"value":"Microelectronics Journal","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107282","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Elsevier Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}],"article-number":"107282"}}