{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T14:21:02Z","timestamp":1783606862695,"version":"3.55.0"},"reference-count":28,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"funder":[{"DOI":"10.13039\/501100004826","name":"Beijing Natural Science Foundation","doi-asserted-by":"publisher","award":["4264149"],"award-info":[{"award-number":["4264149"]}],"id":[{"id":"10.13039\/501100004826","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004826","name":"Beijing Natural Science Foundation","doi-asserted-by":"publisher","award":["4262092"],"award-info":[{"award-number":["4262092"]}],"id":[{"id":"10.13039\/501100004826","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microelectronics Journal"],"published-print":{"date-parts":[[2026,9]]},"DOI":"10.1016\/j.mejo.2026.107296","type":"journal-article","created":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T23:42:17Z","timestamp":1780443737000},"page":"107296","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["A stress-recovered bottom dielectric isolation scheme for GAA nanosheet transistors with self-aligned backside contact integration"],"prefix":"10.1016","volume":"175","author":[{"given":"Shiqi","family":"Cao","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Haoyan","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Longyu","family":"Sun","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiawei","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fei","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yongkui","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yongliang","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"78","reference":[{"key":"10.1016\/j.mejo.2026.107296_bib1","series-title":"2017 Symposium on VLSI Technology","first-page":"T230","article-title":"Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET","author":"Loubet","year":"2017"},{"key":"10.1016\/j.mejo.2026.107296_bib2","series-title":"2013 IEEE International Electron Devices Meeting","first-page":"26.5.1","article-title":"A practical Si nanowire technology with nanowire-on-insulator structure for beyond 10nm logic technologies","author":"Hur","year":"2013"},{"key":"10.1016\/j.mejo.2026.107296_bib3","doi-asserted-by":"crossref","DOI":"10.1016\/j.micrna.2025.208239","article-title":"Development and comparative analysis of a GAA nanosheet FET across diverse space charge region materials for nanoscale applications","volume":"206","author":"Panigrahy","year":"2025","journal-title":"Micro Nanostruct."},{"issue":"4","key":"10.1016\/j.mejo.2026.107296_bib4","doi-asserted-by":"crossref","first-page":"668","DOI":"10.1109\/LED.2026.3659097","article-title":"Matched threshold voltage of n-Si\/p-SiGe hybrid-channel gate-all-around CMOS transistors using a single LaFMD dipole with the same n-Type metal gate","volume":"47","author":"Wang","year":"2026","journal-title":"IEEE Electron Device Lett."},{"key":"10.1016\/j.mejo.2026.107296_bib5","doi-asserted-by":"crossref","first-page":"102","DOI":"10.1109\/OJNANO.2025.3611532","article-title":"Gate stack analysis of junctionless multi-bridge-channel FETs for Sub-3 nm chips","volume":"6","author":"Sreenivasulu","year":"2025","journal-title":"IEEE Open J. Nanotechnol"},{"issue":"21","key":"10.1016\/j.mejo.2026.107296_bib6","doi-asserted-by":"crossref","first-page":"3589","DOI":"10.3390\/electronics11213589","article-title":"A review of the gate-all-around nanosheet FET process opportunities","volume":"11","author":"Mukesh","year":"2022","journal-title":"Electronics"},{"key":"10.1016\/j.mejo.2026.107296_bib7","series-title":"2018 IEEE International Electron Devices Meeting (IEDM)","first-page":"21.3.1","article-title":"Tunability of parasitic channel in gate-all-around stacked nanosheets","author":"Barraud","year":"2018"},{"key":"10.1016\/j.mejo.2026.107296_bib8","series-title":"2016 IEEE Symposium on VLSI Technology","first-page":"1","article-title":"Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates","author":"Mertens","year":"2016"},{"key":"10.1016\/j.mejo.2026.107296_bib9","doi-asserted-by":"crossref","DOI":"10.1016\/j.mejo.2023.106065","article-title":"Novel partial punch-through-stopper scheme for substrate leakage optimization of nanosheet field-effect transistors","volume":"143","author":"Luo","year":"2024","journal-title":"Microelectron. J."},{"key":"10.1016\/j.mejo.2026.107296_bib10","series-title":"2019 IEEE International Electron Devices Meeting (IEDM)","first-page":"11.6.1","article-title":"Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications","author":"Zhang","year":"2019"},{"issue":"8","key":"10.1016\/j.mejo.2026.107296_bib11","doi-asserted-by":"crossref","first-page":"4109","DOI":"10.1109\/TED.2022.3182300","article-title":"Leakage optimization of the buried oxide substrate of nanosheet field-effect transistors","volume":"69","author":"Yoo","year":"2022","journal-title":"IEEE Trans. Electron. Dev."},{"issue":"5","key":"10.1016\/j.mejo.2026.107296_bib12","doi-asserted-by":"crossref","first-page":"2844","DOI":"10.1109\/TED.2024.3373723","article-title":"Analysis of nanosheet field-effect transistor with local bottom isolation","volume":"71","author":"You","year":"2024","journal-title":"IEEE Trans. Electron. Dev."},{"key":"10.1016\/j.mejo.2026.107296_bib13","series-title":"2019 IEEE International Electron Devices Meeting (IEDM)","first-page":"19.1.1","article-title":"Buried power rails and back-side power grids: arm CPU power delivery network design beyond 5nm","author":"Prasad","year":"2019"},{"key":"10.1016\/j.mejo.2026.107296_bib14","series-title":"2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","first-page":"1","article-title":"PPA and scaling potential of backside power options in N2 and A14 nanosheet technology","author":"Yang","year":"2023"},{"key":"10.1016\/j.mejo.2026.107296_bib15","series-title":"2024 IEEE International Electron Devices Meeting (IEDM)","first-page":"1","article-title":"Monolithic-CFET with direct backside contact to source\/drain and backside dielectric isolation","author":"Vandooren","year":"2024"},{"key":"10.1016\/j.mejo.2026.107296_bib16","series-title":"2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","first-page":"1","article-title":"Backside power distribution for nanosheet technologies beyond 2nm","author":"Xie","year":"2024"},{"key":"10.1016\/j.mejo.2026.107296_bib17","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/OJNANO.2024.3365173","article-title":"Analysis of GAA junction less NS FET towards analog and RF applications at 30 nm regime","volume":"5","author":"Panigrahy","year":"2024","journal-title":"IEEE Open J. Nanotechnol"},{"key":"10.1016\/j.mejo.2026.107296_bib18","series-title":"International Roadmap for Devices and Systems (IRDS)","year":"2022"},{"issue":"2","key":"10.1016\/j.mejo.2026.107296_bib19","doi-asserted-by":"crossref","first-page":"86","DOI":"10.4071\/1551-4897-3.2.86","article-title":"A systematic approach to thinning silicon wafers to the sub-40\u03bcm thickness range","volume":"3","author":"Arunasalam","year":"2006","journal-title":"J. Microelectron. Electron. Packag."},{"issue":"11","key":"10.1016\/j.mejo.2026.107296_bib20","article-title":"Selective wet etch of a TaN metal gate with an amorphous-silicon hard mask","volume":"31","author":"Li","year":"2010","journal-title":"J. Semiconduct."},{"issue":"4","key":"10.1016\/j.mejo.2026.107296_bib21","doi-asserted-by":"crossref","DOI":"10.1116\/6.0000711","article-title":"Mechanism of highly selective etching of SiCN by using NF3\/Ar-based plasma","volume":"39","author":"Matsui","year":"2021","journal-title":"J. Vac. Sci. Technol., A"},{"key":"10.1016\/j.mejo.2026.107296_bib22","series-title":"Sentaurus Device User Guide, Synop., Mountain View, CA, USA","year":"2022"},{"key":"10.1016\/j.mejo.2026.107296_bib23","series-title":"2018 IEEE International Electron Devices Meeting (IEDM)","first-page":"28.7.1","article-title":"3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications","author":"Bae","year":"2018"},{"key":"10.1016\/j.mejo.2026.107296_bib24","series-title":"2019 IEEE International Electron Devices Meeting (IEDM)","first-page":"11.5.1","article-title":"Imaging, modeling and engineering of strain in gate-all-around nanosheet transitors","author":"Reboh","year":"2019"},{"key":"10.1016\/j.mejo.2026.107296_bib25","series-title":"2016 IEEE International Electron Devices Meeting (IEDM)","first-page":"17.6.1","article-title":"Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source\/drain","author":"Barraud","year":"2016"},{"issue":"3","key":"10.1016\/j.mejo.2026.107296_bib26","doi-asserted-by":"crossref","first-page":"1497","DOI":"10.1109\/TED.2021.3139579","article-title":"Novel postgate single diffusion break integration in gate-all-around nanosheet transistors to achieve remarkable channel stress for N\/P current matching","volume":"69","author":"Liu","year":"2022","journal-title":"IEEE Trans. Electron. Dev."},{"key":"10.1016\/j.mejo.2026.107296_bib27","series-title":"2008 IEEE International Electron Devices Meeting","first-page":"1","article-title":"High performance Hi-K + metal gate strain enhanced transistors on (110) silicon","author":"Packan","year":"2008"},{"key":"10.1016\/j.mejo.2026.107296_bib28","doi-asserted-by":"crossref","first-page":"73160","DOI":"10.1109\/ACCESS.2024.3392621","article-title":"Spacer dielectric analysis of multi-channel nanosheet FET for nanoscale applications","volume":"12","author":"Panigrahy","year":"2024","journal-title":"IEEE Access"}],"container-title":["Microelectronics Journal"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126002523?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126002523?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T13:44:23Z","timestamp":1783604663000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1879239126002523"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,9]]},"references-count":28,"alternative-id":["S1879239126002523"],"URL":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107296","relation":{},"ISSN":["1879-2391"],"issn-type":[{"value":"1879-2391","type":"print"}],"subject":[],"published":{"date-parts":[[2026,9]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A stress-recovered bottom dielectric isolation scheme for GAA nanosheet transistors with self-aligned backside contact integration","name":"articletitle","label":"Article Title"},{"value":"Microelectronics Journal","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107296","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Elsevier Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}],"article-number":"107296"}}