{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T14:19:07Z","timestamp":1783606747142,"version":"3.55.0"},"reference-count":20,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,9,1]],"date-time":"2026-09-01T00:00:00Z","timestamp":1788220800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T00:00:00Z","timestamp":1780358400000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62,574,222"],"award-info":[{"award-number":["62,574,222"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microelectronics Journal"],"published-print":{"date-parts":[[2026,9]]},"DOI":"10.1016\/j.mejo.2026.107298","type":"journal-article","created":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T23:33:24Z","timestamp":1780356804000},"page":"107298","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["Stability analysis of type-II sampling and subsampling phase-locked loops\u2606"],"prefix":"10.1016","volume":"175","author":[{"given":"Tianle","family":"Chen","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ruocun","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xiaoyu","family":"Shan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hongyu","family":"Ren","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Kai","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xuan","family":"Guo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yunbo","family":"Huang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Li","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zunsong","family":"Yang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bo","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"78","reference":[{"issue":"4","key":"10.1016\/j.mejo.2026.107298_bib1","doi-asserted-by":"crossref","first-page":"1381","DOI":"10.1109\/TCSI.2021.3057580","article-title":"Jitter-power trade-offs in PLLs","volume":"68","author":"Razavi","year":"2021","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"10.1016\/j.mejo.2026.107298_bib2","first-page":"1","article-title":"A 22.4-25.6-GHz ping-pong sub-sampling PLL featuring unified supply voltage level and balanced 2nd harmonic extraction","author":"Huang","year":"2025","journal-title":"IEEE J. Solid-State Circuits early access"},{"key":"10.1016\/j.mejo.2026.107298_bib3","series-title":"2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits","first-page":"1","article-title":"A 6.5-to-6.9 GHz SSPLL with configurable differential dual-edge SSPD achieving 44fs RMS jitter, \u2013260.7dB FOMJitter, and \u201376.5dBc reference spur","author":"Chen","year":"2024"},{"key":"10.1016\/j.mejo.2026.107298_bib4","series-title":"2024 IEEE European Solid-State Electronics Research Conference, ESSERC","first-page":"113","article-title":"A Type-II reference-sampling PLL with non-uniform octuple-sampling phase detector achieving 55-fs JitterRMS, \u201391.9-dBc reference spur and \u2013259-dB jitter-power FoM","author":"Ren","year":"2024"},{"issue":"5","key":"10.1016\/j.mejo.2026.107298_bib5","doi-asserted-by":"crossref","first-page":"548","DOI":"10.1109\/LMWT.2024.3377117","article-title":"A 6-GHz 78-fsRMS double-sampling PLL with low-ripple bootstrapped DSPD and retimer-less MMD achieving \u221292-dBc reference spur and \u2212258-dB FoM","volume":"34","author":"Ren","year":"2024","journal-title":"IEEE Microw. Wireless Technol. Lett."},{"issue":"6","key":"10.1016\/j.mejo.2026.107298_bib6","doi-asserted-by":"crossref","first-page":"1597","DOI":"10.1109\/JSSC.2022.3225105","article-title":"A 20-GHz PLL with 20.9-fs random jitter","volume":"58","author":"Zhao","year":"2023","journal-title":"IEEE J. Solid State Circ."},{"key":"10.1016\/j.mejo.2026.107298_bib7","series-title":"2019 IEEE International Solid-State Circuits Conference","first-page":"270","article-title":"16.8 A 25.4-to-29.5 GHz 10.2 mW isolated sub-sampling PLL achieving-252.9 dB jitter-power FoM and -63dBc reference spur","author":"Yang","year":"2019"},{"issue":"2","key":"10.1016\/j.mejo.2026.107298_bib8","doi-asserted-by":"crossref","first-page":"238","DOI":"10.1109\/TVLSI.2021.3131219","article-title":"A 3.3-GHz integer N-type-II sub-sampling PLL using a BFSK-Suppressed push\u2013pull SS-PD and a fast-locking FLL achieving \u221282.2-dBc REF spur and \u2212255-dB FoM","volume":"30","author":"Yang","year":"2022","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"12","key":"10.1016\/j.mejo.2026.107298_bib9","doi-asserted-by":"crossref","first-page":"3253","DOI":"10.1109\/JSSC.2009.2032723","article-title":"A low noise sub-sampling PLL in which divider noise is eliminated and PD\/CP noise is not multiplied by N2","volume":"44","author":"Gao","year":"2009","journal-title":"IEEE J. Solid State Circ."},{"issue":"9","key":"10.1016\/j.mejo.2026.107298_bib10","doi-asserted-by":"crossref","first-page":"1809","DOI":"10.1109\/JSSC.2010.2053094","article-title":"Spur reduction techniques for phase-locked loops exploiting a sub-sampling phase detector","volume":"45","author":"Gao","year":"2010","journal-title":"IEEE J. Solid State Circ."},{"issue":"6","key":"10.1016\/j.mejo.2026.107298_bib11","first-page":"1665","article-title":"A 0.65-V 12\u201316-GHz sub-sampling PLL with 56.4-fsrms integrated jitter and \u2212256.4-dB FoM","volume":"55","author":"Zhang","year":"2020","journal-title":"IEEE J. Solid State Circ."},{"key":"10.1016\/j.mejo.2026.107298_bib12","series-title":"2023 IEEE Asian Solid-State Circuits Conference, A-SSCC","first-page":"1","article-title":"A 12.75-to-16-GHz spur-jitter-joint-optimization SS-PLL achieving -94.55-dBc reference spur, 31.9-fs integrated jitter and -260.1-dB FoM","author":"Li","year":"2023"},{"issue":"12","key":"10.1016\/j.mejo.2026.107298_bib13","doi-asserted-by":"crossref","first-page":"3952","DOI":"10.1109\/JSSC.2024.3458463","article-title":"A 23.2-to-26-GHz low-jitter fast-locking sub-sampling PLL based on a function-reused VCO-Buffer and a type-I FLL with rapid phase alignment","volume":"59","author":"Li","year":"2024","journal-title":"IEEE J. Solid State Circ."},{"issue":"2","key":"10.1016\/j.mejo.2026.107298_bib14","doi-asserted-by":"crossref","first-page":"480","DOI":"10.1109\/JSSC.2021.3116149","article-title":"A wide-lock-in-range and low-jitter 12\u201314.5 GHz SSPLL using a low-power frequency-disturbance-detecting and correcting loop","volume":"57","author":"Lim","year":"2022","journal-title":"IEEE J. Solid State Circ."},{"issue":"5","key":"10.1016\/j.mejo.2026.107298_bib15","doi-asserted-by":"crossref","first-page":"780","DOI":"10.1109\/4.841507","article-title":"A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver","volume":"35","author":"Rategh","year":"2000","journal-title":"IEEE J. Solid State Circ."},{"key":"10.1016\/j.mejo.2026.107298_bib16","first-page":"1","article-title":"An analysis and performance evaluation of a passive filter design technique for charge pump phase-locked loops","volume":"1001","author":"O Keese","year":"1996","journal-title":"National Semiconductor Application Note"},{"issue":"4","key":"10.1016\/j.mejo.2026.107298_bib17","first-page":"1351","article-title":"Universal stability criterion for type-I sampling phase-locked loops","volume":"70","author":"Huang","year":"2023","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"issue":"7","key":"10.1016\/j.mejo.2026.107298_bib18","first-page":"3159","article-title":"A closed-form transfer function for sample and hold master slave sampling filter","volume":"69","author":"Abdekhoda","year":"2022","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"10.1016\/j.mejo.2026.107298_bib19","series-title":"2019 IEEE European Solid-State Circuits Conference, ESSCIRC, Tutorial","article-title":"Ultra-low-power DTC-Based fractional-N digital PLL techniques","author":"Okada","year":"2019"},{"issue":"3","key":"10.1016\/j.mejo.2026.107298_bib20","doi-asserted-by":"crossref","first-page":"626","DOI":"10.1109\/JSSC.2015.2511157","article-title":"A 2.4 GHz 4 mW integer-N inductorless RF synthesizer","volume":"51","author":"Kong","year":"2016","journal-title":"IEEE J. Solid State Circ."}],"container-title":["Microelectronics Journal"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126002547?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126002547?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,7,9]],"date-time":"2026-07-09T13:41:56Z","timestamp":1783604516000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1879239126002547"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,9]]},"references-count":20,"alternative-id":["S1879239126002547"],"URL":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107298","relation":{},"ISSN":["1879-2391"],"issn-type":[{"value":"1879-2391","type":"print"}],"subject":[],"published":{"date-parts":[[2026,9]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Stability analysis of type-II sampling and subsampling phase-locked loops\u2606","name":"articletitle","label":"Article Title"},{"value":"Microelectronics Journal","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107298","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 The Authors. Published by Elsevier Ltd.","name":"copyright","label":"Copyright"}],"article-number":"107298"}}