{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,10]],"date-time":"2026-08-10T21:29:45Z","timestamp":1786397385757,"version":"build-2736575974"},"reference-count":31,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T00:00:00Z","timestamp":1790812800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"funder":[{"DOI":"10.13039\/501100012401","name":"Beijing Science and Technology Planning Project","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100012401","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Microelectronics Journal"],"published-print":{"date-parts":[[2026,10]]},"DOI":"10.1016\/j.mejo.2026.107388","type":"journal-article","created":{"date-parts":[[2026,7,20]],"date-time":"2026-07-20T08:53:10Z","timestamp":1784537590000},"page":"107388","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["A time-domain compute-in-memory macro with binary-gated dual-edge cell and low-power truncation TDC"],"prefix":"10.1016","volume":"176","author":[{"ORCID":"https:\/\/orcid.org\/0009-0000-7904-9605","authenticated-orcid":false,"given":"Jinyu","family":"Gao","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mingrui","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wenhui","family":"Shi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Long","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ye","family":"Zhao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shushan","family":"Qiao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"78","reference":[{"issue":"7","key":"10.1016\/j.mejo.2026.107388_b1","doi-asserted-by":"crossref","first-page":"1888","DOI":"10.1109\/JSSC.2020.2992886","article-title":"C3SRAM: An in-memory-computing SRAM macro based on robust capacitive coupling computing mechanism","volume":"55","author":"Jiang","year":"2020","journal-title":"IEEE J. Solid-State Circuits"},{"key":"10.1016\/j.mejo.2026.107388_b2","series-title":"2019 Symposium on VLSI Circuits","first-page":"C248","article-title":"A ternary based bit scalable, 8.80 TOPS\/W CNN accelerator with many-core processing-in-memory architecture with 896k synapses\/mm 2","author":"Okumura","year":"2019"},{"key":"10.1016\/j.mejo.2026.107388_b3","series-title":"2018 IEEE International Solid-State Circuits Conference","first-page":"488","article-title":"Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications","author":"Biswas","year":"2018"},{"issue":"4","key":"10.1016\/j.mejo.2026.107388_b4","doi-asserted-by":"crossref","first-page":"915","DOI":"10.1109\/JSSC.2016.2642198","article-title":"In-memory computation of a machine-learning classifier in a standard 6T SRAM array","volume":"52","author":"Zhang","year":"2017","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"4","key":"10.1016\/j.mejo.2026.107388_b5","doi-asserted-by":"crossref","first-page":"1009","DOI":"10.1109\/JSSC.2016.2515510","article-title":"A 28 nm configurable memory (TCAM\/BCAM\/SRAM) using push-rule 6T bit cell enabling logic-in-memory","volume":"51","author":"Jeloka","year":"2016","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"5","key":"10.1016\/j.mejo.2026.107388_b6","doi-asserted-by":"crossref","first-page":"1773","DOI":"10.1109\/TCSI.2021.3064189","article-title":"Challenges and trends of SRAM-based computing-in-memory for AI edge devices","volume":"68","author":"Jhang","year":"2021","journal-title":"IEEE Trans. Circuits Syst. I. Regul. Pap."},{"issue":"6","key":"10.1016\/j.mejo.2026.107388_b7","first-page":"1733","article-title":"XNOR-SRAM: In-memory computing SRAM macro for binary\/ternary deep neural networks","volume":"55","author":"Yin","year":"2020","journal-title":"IEEE J. Solid-State Circuits"},{"key":"10.1016\/j.mejo.2026.107388_b8","series-title":"2024 IEEE 6th International Conference on AI Circuits and Systems","first-page":"184","article-title":"An area and energy-efficient sram based time-domain compute-in-memory architecture for bnn","author":"Chakraborty","year":"2024"},{"issue":"1","key":"10.1016\/j.mejo.2026.107388_b9","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/TVLSI.2020.3020286","article-title":"Mixed-signal computing for deep neural network inference","volume":"29","author":"Murmann","year":"2020","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"issue":"10","key":"10.1016\/j.mejo.2026.107388_b10","doi-asserted-by":"crossref","first-page":"2944","DOI":"10.1109\/JSSC.2022.3182699","article-title":"FlashMAC: A time-frequency hybrid MAC architecture with variable latency-aware scheduling for TinyML systems","volume":"57","author":"Gweon","year":"2022","journal-title":"IEEE J. Solid-State Circuits"},{"key":"10.1016\/j.mejo.2026.107388_b11","series-title":"2024 IEEE International Symposium on Circuits and Systems","first-page":"1","article-title":"SRAM-based hybrid analog compute-in-memory architecture to enhance the signal margin","author":"Kushwaha","year":"2024"},{"issue":"15","key":"10.1016\/j.mejo.2026.107388_b12","doi-asserted-by":"crossref","DOI":"10.1587\/elex.22.20250317","article-title":"An SRAM-based chunked computing-in-memory macro with a multi-slope voltage-time-digital converting ADC for efficient MAC operations","volume":"22","author":"Li","year":"2025","journal-title":"IEICE Electron. Express"},{"key":"10.1016\/j.mejo.2026.107388_b13","series-title":"2024 IEEE Asian Solid-State Circuits Conference","first-page":"1","article-title":"A 28-nm 323 TOPS\/mm 2\/b and 2007 TOPS\/W\/b ternary latch based sparsity-aware CIM macro with double-sampling ternary ADC","author":"Kim","year":"2024"},{"key":"10.1016\/j.mejo.2026.107388_b14","article-title":"A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications","volume":"126","author":"Xiao","year":"2022","journal-title":"Microelectron. J."},{"key":"10.1016\/j.mejo.2026.107388_b15","doi-asserted-by":"crossref","unstructured":"Yuyao Kong, Jun Yang, In-memory Processing based on Time-domain Circuit, in: Proceedings of the 2019 Great Lakes Symposium on VLSI, 2019, pp. 435\u2013438.","DOI":"10.1145\/3299874.3319484"},{"key":"10.1016\/j.mejo.2026.107388_b16","doi-asserted-by":"crossref","unstructured":"Dhandeep Challagundla, Ignatius Bezzam, Riadul Islam, A resonant time-domain compute-in-memory (rTD-CiM) ADC-less architecture for MAC operations, in: Proceedings of the Great Lakes Symposium on VLSI 2024, 2024, pp. 268\u2013271.","DOI":"10.1145\/3649476.3658773"},{"issue":"8","key":"10.1016\/j.mejo.2026.107388_b17","doi-asserted-by":"crossref","first-page":"3377","DOI":"10.1109\/TCSI.2021.3083275","article-title":"TD-SRAM: Time-domain-based in-memory computing macro for binary neural networks","volume":"68","author":"Song","year":"2021","journal-title":"IEEE Trans. Circuits Syst. I. Regul. Pap."},{"issue":"5","key":"10.1016\/j.mejo.2026.107388_b18","first-page":"2789","article-title":"A 768.7-2124.2 TOPS\/W time-domain computing-in-memory macro with low static leakage and precision-configurable TDC","volume":"71","author":"Xue","year":"2023","journal-title":"IEEE Trans. Circuits Syst. II: Express Briefs"},{"issue":"10","key":"10.1016\/j.mejo.2026.107388_b19","doi-asserted-by":"crossref","first-page":"3908","DOI":"10.1109\/TCSI.2023.3294181","article-title":"Tdpro: Time-domain-based computing-in memory engine for ultra-low power ecg processor","volume":"70","author":"Chang","year":"2023","journal-title":"IEEE Trans. Circuits Syst. I. Regul. Pap."},{"issue":"10","key":"10.1016\/j.mejo.2026.107388_b20","doi-asserted-by":"crossref","first-page":"3021","DOI":"10.1109\/JSSC.2021.3095232","article-title":"TIMAQ: A time-domain computing-in-memory-based processor using predictable decomposed convolution for arbitrary quantized DNNs","volume":"56","author":"Yang","year":"2021","journal-title":"IEEE J. Solid-State Circuits"},{"issue":"1","key":"10.1016\/j.mejo.2026.107388_b21","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/TCSI.2024.3480350","article-title":"A 701.7 TOPS\/W Compute-in-Memory processor with time-domain computing for spiking neural network","volume":"72","author":"Park","year":"2024","journal-title":"IEEE Trans. Circuits Syst. I. Regul. Pap."},{"key":"10.1016\/j.mejo.2026.107388_b22","series-title":"2019 IEEE International Solid-State Circuits Conference","first-page":"394","article-title":"24.4 Sandwich-RAM: An energy-efficient in-memory BWN architecture with pulse-width modulation","author":"Yang","year":"2019"},{"issue":"7","key":"10.1016\/j.mejo.2026.107388_b23","doi-asserted-by":"crossref","first-page":"2297","DOI":"10.1109\/JSSC.2023.3343669","article-title":"An 8b-precision 6T SRAM computing-in-memory macro using time-domain incremental accumulation for AI edge chips","volume":"59","author":"Wu","year":"2023","journal-title":"IEEE J. Solid-State Circuits"},{"key":"10.1016\/j.mejo.2026.107388_b24","series-title":"2022 IEEE Custom Integrated Circuits Conference","first-page":"1","article-title":"DCT-RAM: A driver-free process-in-memory 8T SRAM macro with multi-bit charge-domain computation and time-domain quantization","author":"Chen","year":"2022"},{"key":"10.1016\/j.mejo.2026.107388_b25","series-title":"2024 IEEE Custom Integrated Circuits Conference","first-page":"1","article-title":"A 28nm 314.6 tlfops\/w reconfigurable floating-point analog compute-in-memory macro with exponent approximation and two-stage sharing td-adc","author":"He","year":"2024"},{"key":"10.1016\/j.mejo.2026.107388_b26","series-title":"2020 IEEE Nuclear Science Symposium and Medical Imaging Conference","first-page":"1","article-title":"An FPGA-based, high-precision, narrow pulse width measurement time-to-digital converter","author":"Wu","year":"2020"},{"key":"10.1016\/j.mejo.2026.107388_b27","doi-asserted-by":"crossref","first-page":"221","DOI":"10.1016\/j.neunet.2021.10.018","article-title":"Sparsity-control ternary weight networks","volume":"145","author":"Deng","year":"2022","journal-title":"Neural Netw."},{"issue":"3","key":"10.1016\/j.mejo.2026.107388_b28","doi-asserted-by":"crossref","first-page":"781","DOI":"10.1109\/TCAD.2022.3184276","article-title":"FAT: An in-memory accelerator with fast addition for ternary weight neural networks","volume":"42","author":"Zhu","year":"2022","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"10.1016\/j.mejo.2026.107388_b29","doi-asserted-by":"crossref","DOI":"10.1109\/LSSC.2025.3558928","article-title":"A segmented precision configurable computing-in-memory macro with dual-edge time-domain structure","author":"Xue","year":"2025","journal-title":"IEEE Solid-State Circuits Lett."},{"key":"10.1016\/j.mejo.2026.107388_b30","series-title":"2024 IEEE International Symposium on Circuits and Systems","first-page":"1","article-title":"PVT-insensitive time-domain-based in-memory computation with improved linearity for binary neural networks","author":"Singh","year":"2024"},{"key":"10.1016\/j.mejo.2026.107388_b31","series-title":"Signed binary weight networks","author":"Kuhar","year":"2022"}],"container-title":["Microelectronics Journal"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126003449?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1879239126003449?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,8,10]],"date-time":"2026-08-10T20:57:47Z","timestamp":1786395467000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1879239126003449"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,10]]},"references-count":31,"alternative-id":["S1879239126003449"],"URL":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107388","relation":{},"ISSN":["1879-2391"],"issn-type":[{"value":"1879-2391","type":"print"}],"subject":[],"published":{"date-parts":[[2026,10]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"A time-domain compute-in-memory macro with binary-gated dual-edge cell and low-power truncation TDC","name":"articletitle","label":"Article Title"},{"value":"Microelectronics Journal","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.mejo.2026.107388","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Elsevier Ltd. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}],"article-number":"107388"}}