{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,6]],"date-time":"2026-05-06T20:14:43Z","timestamp":1778098483078,"version":"3.51.4"},"reference-count":29,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"funder":[{"DOI":"10.13039\/501100004083","name":"Ministry of Science ICT and Future Planning","doi-asserted-by":"publisher","award":["NRF-2022M3C1A3081366"],"award-info":[{"award-number":["NRF-2022M3C1A3081366"]}],"id":[{"id":"10.13039\/501100004083","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100004358","name":"Samsung Electronics Co Ltd","doi-asserted-by":"publisher","award":["MEM210728_0001"],"award-info":[{"award-number":["MEM210728_0001"]}],"id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100015499","name":"Jeonbuk National University","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100015499","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100014188","name":"Korea Ministry of Science and ICT","doi-asserted-by":"publisher","award":["2021R1G1A1091369"],"award-info":[{"award-number":["2021R1G1A1091369"]}],"id":[{"id":"10.13039\/501100014188","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Physical Communication"],"published-print":{"date-parts":[[2026,5]]},"DOI":"10.1016\/j.phycom.2026.103067","type":"journal-article","created":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T00:31:59Z","timestamp":1773361919000},"page":"103067","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["New design of spotty and adjacent symbol error correction codes for high-speed interconnects"],"prefix":"10.1016","volume":"76","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8916-8955","authenticated-orcid":false,"given":"Chanki","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3946-0958","authenticated-orcid":false,"given":"Jong-Seon","family":"No","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"issue":"4","key":"10.1016\/j.phycom.2026.103067_bib0001","doi-asserted-by":"crossref","first-page":"2758","DOI":"10.1109\/COMST.2018.2839672","article-title":"Survey of photonic and plasmonic interconnect technologies for intra-datacenter and high-performance computing communications","volume":"20","author":"Thraskias","year":"2018","journal-title":"IEEE Comm. Sur. Tutor."},{"issue":"1","key":"10.1016\/j.phycom.2026.103067_bib0002","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1109\/MM.2020.3039925","article-title":"PCI express 6.0 specification: a low-latency, high-bandwidth, high-reliability, and cost-effective interconnect with 64.0 GT\/s PAM-4 signaling","volume":"41","author":"Sharma","year":"2021","journal-title":"IEEE Micro"},{"key":"10.1016\/j.phycom.2026.103067_bib0003","series-title":"Code Design for Dependable System: Theory and Practical Applications","author":"Fujiwara","year":"2006"},{"key":"10.1016\/j.phycom.2026.103067_bib0004","series-title":"IEEE Int\u2019l Symp. High Perf. Comp. Arch. (HPCA)","first-page":"61","article-title":"Defect analysis and cost-effective resilience architecture for future DRAM devices","author":"Cha","year":"2017"},{"issue":"1","key":"10.1016\/j.phycom.2026.103067_bib0005","article-title":"A 1.1-V 10-nm class 6.4-Gb\/s\/pin 16-Gb DDR5 SDRAM with a phase rotator-ILO DLL, high-speed serDes, and DFE\/FFE equalization scheme for Rx\/Tx","volume":"55","author":"Kim","year":"2020","journal-title":"IEEE Jour. Sol. Circ."},{"key":"10.1016\/j.phycom.2026.103067_bib0006","series-title":"IEEE Symp. VLSI Tech. and Circ.","first-page":"166","article-title":"A 16 GB 1024 GB\/s HBM3 DRAM with on-die error control scheme for enhanced RAS features","author":"Ryu","year":"2022"},{"key":"10.1016\/j.phycom.2026.103067_bib0007","series-title":"Annual IEEE\/IFIP Int\u2019l Conf. on Dep. Syst. and Net. (ICDSN)","article-title":"Revisiting memory errors in large-scale production data centers: analysis and modeling of new trends from the field","author":"Meza","year":"2015"},{"key":"10.1016\/j.phycom.2026.103067_bib0008","series-title":"Supercomputing Conference (SC), Proc. of the Int.l Conf. for High Perf. Comp., Net., Storage and Anal","article-title":"Unprotected computing: a large-scale study of DRAM raw error rate on a supercomputer","author":"Bautista-Gomez","year":"2016"},{"key":"10.1016\/j.phycom.2026.103067_bib0009","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1016\/j.microrel.2019.03.012","article-title":"Low delay single error correction and double adjacent error correction (SEC-DAEC) codes","volume":"97","author":"Li","year":"2019","journal-title":"Microelectron. Reliab."},{"issue":"6","key":"10.1016\/j.phycom.2026.103067_bib0010","doi-asserted-by":"crossref","first-page":"823","DOI":"10.1007\/s00542-023-05464-3","article-title":"Single and double-adjacent error correcting code (SDECC) with lower design overheads and mis-correction rate for SRAMs","volume":"29","author":"Maity","year":"2023","journal-title":"Microsyst. Technol."},{"key":"10.1016\/j.phycom.2026.103067_bib0011","series-title":"IEEE VLSI Test Symp. (VTS)","article-title":"Multiple bit upset tolerant memory using a selective cycle avoidance based SEC-DED-DAEC codes","author":"Dutta","year":"2007"},{"issue":"3","key":"10.1016\/j.phycom.2026.103067_bib0012","doi-asserted-by":"crossref","first-page":"884","DOI":"10.1109\/TDMR.2014.2332364","article-title":"A method to design SEC-DED-DAEC codes with optimized decoding","volume":"14","author":"Reviriego","year":"2014","journal-title":"IEEE Trans Dev. And Mat. Reliab."},{"issue":"8","key":"10.1016\/j.phycom.2026.103067_bib0013","doi-asserted-by":"crossref","DOI":"10.1109\/TC.1984.5009359","article-title":"A class of odd-weight-column SEC-DED-SbED codes for memory system applications","volume":"33","author":"Kaneda","year":"1984","journal-title":"IEEE Trans. Comp."},{"issue":"1","key":"10.1016\/j.phycom.2026.103067_bib0014","doi-asserted-by":"crossref","first-page":"574","DOI":"10.1109\/TDMR.2012.2204753","article-title":"Hamming SEC-DAED and extended hamming SEC-DED-TAED codes through selective shortening and bit placement","volume":"14","author":"Sanchez-Macian","year":"2014","journal-title":"IEEE Trans. Device Mater. Reliab."},{"key":"10.1016\/j.phycom.2026.103067_bib0015","doi-asserted-by":"crossref","first-page":"89769","DOI":"10.1109\/ACCESS.2022.3201525","article-title":"SEC-BADAEC: an efficient ECC with no vacancy for strong memory protection","volume":"10","author":"Song","year":"2022","journal-title":"IEEE Access"},{"key":"10.1016\/j.phycom.2026.103067_bib0016","series-title":"Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)","article-title":"Exploring and optimizing chipkill-correct for persistent memory based on high-density NVRAMs","author":"Zhang","year":"2018"},{"key":"10.1016\/j.phycom.2026.103067_bib0017","series-title":"IEEE 802 Plenary","article-title":"10GBASE-KR FEC tutorial","author":"Szczepanek","year":"2006"},{"key":"10.1016\/j.phycom.2026.103067_bib0018","series-title":"IEEE Communications Standards Magazine","article-title":"Analysis and comparison of FEC schemes for 200GbE and 400GbE","author":"Wang","year":"2017"},{"key":"10.1016\/j.phycom.2026.103067_bib0019","series-title":"PAM4 signals testing considerations: Learning from PCIe and Ethernet\/OIF-CEI for 100 Gb\/s per Lane","author":"Nourzad","year":"2024"},{"key":"10.1016\/j.phycom.2026.103067_bib0020","unstructured":"H. Shakiba, Error Propagation Analysis of MLSE, IEEE standard 802.3dj, 2023. https:\/\/www.ieee802.org\/3\/dj\/public\/adhoc\/electrical\/23_0420\/shakiba_3dj_elec_02_230420.pdf."},{"key":"10.1016\/j.phycom.2026.103067_bib0021","series-title":"DesignCon 2025","article-title":"Post-FEC BER analysis of 200 gb\/s wireline systems using an FPGA platform","author":"Barrie","year":"2025"},{"issue":"7","key":"10.1016\/j.phycom.2026.103067_bib0022","first-page":"406","article-title":"Binary locally repairable codes with minimum distance at least six based on partial t-spreads","volume":"21","author":"Nam","year":"2017","journal-title":"IEEE Comm. Lett."},{"issue":"2","key":"10.1016\/j.phycom.2026.103067_bib0023","doi-asserted-by":"crossref","first-page":"228","DOI":"10.1109\/LCOMM.2017.2776141","article-title":"New constructions of binary and ternary locally repairable codes using cyclic codes","volume":"22","author":"Kim","year":"2018","journal-title":"IEEE Comm. Lett."},{"issue":"3","key":"10.1016\/j.phycom.2026.103067_bib0024","doi-asserted-by":"crossref","first-page":"406","DOI":"10.1109\/LCOMM.2019.2892950","article-title":"New constructions of binary LRCs with disjoint repair groups and locality 3 using existing LRCs","volume":"23","author":"Kim","year":"2019","journal-title":"IEEE Comm. Lett."},{"key":"10.1016\/j.phycom.2026.103067_sbref0025","series-title":"Technical Report","article-title":"Evaluation of FEC Performance with Symbol and Bit-Muxing Scenarios","author":"Wang","year":"2014"},{"issue":"4","key":"10.1016\/j.phycom.2026.103067_bib0026","first-page":"1","article-title":"FPGA HLS today: successes, challenges, and opportunities","volume":"15","author":"Cong","year":"2022","journal-title":"ACM Trans. Recon. Tech. Syst."},{"key":"10.1016\/j.phycom.2026.103067_bib0027","unstructured":"S. Cui, A. Patke, H. Nguyen, A. Ranjan, Z. Chen, P. Cao, B. Bode, G. Bauer, C.D. Martinao, S. Jha, C. Narayanaswami, D. Sow, Z.T. Kalbarczyk, R.K. Iyer, Characterizing GPU Resilience and impact on AI\/HPC systems, arXiv: 2503.11901v3 [cs.dc], 2025."},{"key":"10.1016\/j.phycom.2026.103067_bib0028","series-title":"IEEE Intl Symp. Microarchitecture (MICRO)","first-page":"930","article-title":"Heterogeneous die-to-die interfaces: enabling more flexible chiplet interconnection systems","author":"Feng","year":"2023"},{"issue":"10","key":"10.1016\/j.phycom.2026.103067_bib0029","doi-asserted-by":"crossref","first-page":"783","DOI":"10.1364\/JOCN.496992","article-title":"The future of communications is massively parallel","volume":"15","author":"Winzer","year":"2023","journal-title":"J. Opt. Commun. Netw."}],"container-title":["Physical Communication"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1874490726000765?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1874490726000765?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,5,6]],"date-time":"2026-05-06T19:41:30Z","timestamp":1778096490000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1874490726000765"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5]]},"references-count":29,"alternative-id":["S1874490726000765"],"URL":"https:\/\/doi.org\/10.1016\/j.phycom.2026.103067","relation":{},"ISSN":["1874-4907"],"issn-type":[{"value":"1874-4907","type":"print"}],"subject":[],"published":{"date-parts":[[2026,5]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"New design of spotty and adjacent symbol error correction codes for high-speed interconnects","name":"articletitle","label":"Article Title"},{"value":"Physical Communication","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.phycom.2026.103067","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Elsevier B.V. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}],"article-number":"103067"}}