{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,12]],"date-time":"2026-03-12T00:00:29Z","timestamp":1773273629464,"version":"3.50.1"},"reference-count":106,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[2026,5]]},"DOI":"10.1016\/j.vlsi.2026.102665","type":"journal-article","created":{"date-parts":[[2026,1,14]],"date-time":"2026-01-14T16:52:50Z","timestamp":1768409570000},"page":"102665","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["Clock tree synthesis in modern VLSI: From foundational algorithms to AI-driven optimization"],"prefix":"10.1016","volume":"108","author":[{"given":"Manikandan","family":"B","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4749-2343","authenticated-orcid":false,"given":"Karthikumar","family":"S","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"issue":"20","key":"10.1016\/j.vlsi.2026.102665_bib1","doi-asserted-by":"crossref","first-page":"4340","DOI":"10.3390\/electronics12204340","article-title":"Shallow clock tree pre-estimation for designing clock tree synthesizable verilog RTLs","volume":"12","author":"Kwon","year":"2023","journal-title":"Electronics"},{"key":"10.1016\/j.vlsi.2026.102665_bib2","series-title":"2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)","first-page":"1","article-title":"A technique to optimize clock latency after CCOpt exploiting useful skew","author":"Dhar","year":"2024"},{"issue":"1","key":"10.1016\/j.vlsi.2026.102665_bib3","doi-asserted-by":"crossref","first-page":"142","DOI":"10.1109\/TVLSI.2014.2300174","article-title":"Obstacle-avoiding and slew-constrained clock tree synthesis with efficient buffer insertion","volume":"23","author":"Cai","year":"2014","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"10.1016\/j.vlsi.2026.102665_bib4","series-title":"2024 Global Conference on Communications and Information Technologies (GCCIT)","first-page":"1","article-title":"Design of clock tree distributor with systematic scheduler for stability","author":"Arunkumar","year":"2024"},{"issue":"7","key":"10.1016\/j.vlsi.2026.102665_bib5","doi-asserted-by":"crossref","first-page":"1537","DOI":"10.1109\/TVLSI.2019.2902215","article-title":"Low leakage clock tree with dual-threshold-voltage split input\u2013output repeaters","volume":"27","author":"Gundu","year":"2019","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"10.1016\/j.vlsi.2026.102665_bib6","series-title":"2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD)","first-page":"1","article-title":"Clock aware low power placement","author":"Ding","year":"2023"},{"key":"10.1016\/j.vlsi.2026.102665_bib7","series-title":"2022 2nd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT)","first-page":"249","article-title":"A clock tree synthesis scheme based on flexible H-tree","author":"Wang","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib8","series-title":"2023 7th International Conference on Intelligent Computing and Control Systems (ICICCS)","first-page":"1799","article-title":"Design and implementation of high-performance PnR block-level design with timing placement","author":"Pravin","year":"2023"},{"issue":"1","key":"10.1016\/j.vlsi.2026.102665_bib9","doi-asserted-by":"crossref","first-page":"1","DOI":"10.29292\/jics.v19i1.769","article-title":"Comparative implementation of PicoSoC system-on-chip in X-Fab 180 nm CMOS technology","volume":"19","author":"Wuerdig","year":"2024","journal-title":"Journal of Integrated Circuits and Systems"},{"key":"10.1016\/j.vlsi.2026.102665_bib10","series-title":"2023 14th International Conference on Information and Communication Technology Convergence (ICTC)","first-page":"1572","article-title":"Lightweighted shallow CTS techniques for checking clock tree synthesizable paths and optimizing clock tree in RTL design time","author":"Kwon","year":"2023"},{"key":"10.1016\/j.vlsi.2026.102665_bib11","series-title":"2021 6th International Conference on Communication and Electronics Systems (ICCES)","first-page":"1","article-title":"ASIC design of a 32-bit low power RISC-V based system core for medical applications","author":"Kanase","year":"2021"},{"key":"10.1016\/j.vlsi.2026.102665_bib12","series-title":"2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","first-page":"1","article-title":"A fast security closure approach for EM-based attacks on general multi-segment interconnects","author":"Stoikos","year":"2024"},{"issue":"5","key":"10.1016\/j.vlsi.2026.102665_bib13","first-page":"1","article-title":"A novel clock tree aware placement methodology for single flux quantum logic circuits with maximum path length consideration","volume":"32","author":"Wang","year":"2022","journal-title":"IEEE Trans. Appl. Supercond."},{"issue":"9","key":"10.1016\/j.vlsi.2026.102665_bib14","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TASC.2023.3328921","article-title":"Design automation framework for placement and clock tree synthesis of superconducting rapid single-flux-quantum logic","volume":"33","author":"Yang","year":"2023","journal-title":"IEEE Trans. Appl. Supercond."},{"key":"10.1016\/j.vlsi.2026.102665_bib15","series-title":"Proceedings of the 2022 ACM\/IEEE Workshop on Machine Learning for CAD","first-page":"127","article-title":"Graph representation learning for gate arrival time prediction","author":"Shrestha","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib16","doi-asserted-by":"crossref","DOI":"10.1016\/j.micpro.2023.104913","article-title":"Clock tree generation by abutment in synchoros VLSI design","volume":"102","author":"Stathis","year":"2023","journal-title":"Microprocess. Microsyst."},{"key":"10.1016\/j.vlsi.2026.102665_bib17","series-title":"Proc. SASIMI","first-page":"1","article-title":"A comparative study on multisource clock network synthesis","author":"Chen","year":"2016"},{"key":"10.1016\/j.vlsi.2026.102665_bib18","series-title":"2020 7th International Conference on Smart Structures and Systems (ICSSS)","first-page":"1","article-title":"A Robust CTS algorithm using the H-Tree to minimize local skews of higher frequency targets of the SOC designs","author":"Bhaskara","year":"2020"},{"issue":"8","key":"10.1016\/j.vlsi.2026.102665_bib19","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TASC.2019.2943930","article-title":"A minimum-skew clock tree synthesis algorithm for single flux quantum logic circuits","volume":"29","author":"Shahsavani","year":"2019","journal-title":"IEEE Trans. Appl. Supercond."},{"key":"10.1016\/j.vlsi.2026.102665_bib20","series-title":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","first-page":"276","article-title":"Clock tree synthesis techniques for optimal power and timing convergence in soc partitions","author":"Vishnu","year":"2019"},{"key":"10.1016\/j.vlsi.2026.102665_bib21","series-title":"2023 Second International Conference on Trends in Electrical, Electronics, and Computer Engineering (TEECCON)","first-page":"293","article-title":"Implementation of Routing-denser PnR flow for an efficient IC block level design","author":"Jenila","year":"2023"},{"key":"10.1016\/j.vlsi.2026.102665_bib22","series-title":"Proceedings of the 2014 on International Symposium on Physical Design","first-page":"69","article-title":"Clock tree resynthesis for multi-corner multi-mode timing closure","author":"Roy","year":"2014"},{"issue":"1","key":"10.1016\/j.vlsi.2026.102665_bib23","doi-asserted-by":"crossref","first-page":"142","DOI":"10.1109\/TVLSI.2014.2300174","article-title":"Obstacle-avoiding and slew-constrained clock tree synthesis with efficient buffer insertion","volume":"23","author":"Cai","year":"2014","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"10.1016\/j.vlsi.2026.102665_bib24","series-title":"2020 IEEE International Symposium on Smart Electronic Systems (Ises)(Formerly Inis)","first-page":"312","article-title":"Designing of an optimization technique for the prediction of CTS outcomes using neural network","author":"Nagaria","year":"2020"},{"key":"10.1016\/j.vlsi.2026.102665_bib25","series-title":"2024 International Conference on Smart Electronics and Communication Systems (ISENSE)","first-page":"1","article-title":"Design implementation of synchronous FIFO-Synthesis, PNR, STA and physical verification","author":"Shenoy","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib26","series-title":"2024 IEEE 5th India Council International Subsections Conference (INDISCON)","first-page":"1","article-title":"Efficient RTL to GDS II flow for finite State machine integration: a physical design approach","author":"Shohal","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib27","series-title":"2024 International Conference on Inventive Computation Technologies (ICICT)","first-page":"2013","article-title":"Implementation of a PnR flow at block level to achieve the high utilisation rate","author":"Kadarkarai","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib28","series-title":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","first-page":"1","article-title":"Hybrid multisource clock tree synthesis","author":"Chong","year":"2021"},{"key":"10.1016\/j.vlsi.2026.102665_bib29","series-title":"2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)","first-page":"83","article-title":"iPD: an open-source intelligent physical design toolchain","author":"Li","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib30","series-title":"2023 IEEE East-West Design & Test Symposium (EWDTS)","first-page":"1","article-title":"New approach of IO cell placement addressing minimized data and clock skews in top level","author":"Arman","year":"2023"},{"key":"10.1016\/j.vlsi.2026.102665_bib31","series-title":"2022 23rd International Symposium on Quality Electronic Design (ISQED)","first-page":"1","article-title":"Path-based pre-routing timing prediction for modern very large-scale integration designs","author":"Chen","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib32","series-title":"2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","first-page":"1","article-title":"Performance optimized clock tree embedding for auto-generated FPGAs","author":"Brown","year":"2023"},{"key":"10.1016\/j.vlsi.2026.102665_bib33","series-title":"2012 25th International Conference on VLSI Design","first-page":"233","article-title":"Clock tree skew minimization with structured routing","author":"Chakrabarti","year":"2012"},{"key":"10.1016\/j.vlsi.2026.102665_bib34","series-title":"2015 2nd International Conference on Electrical Information and Communication Technologies (EICT)","first-page":"239","article-title":"Implimentation and evaluation of an efficient clock distribution network for deep-submicron technology","author":"Rahman","year":"2015"},{"issue":"2","key":"10.1016\/j.vlsi.2026.102665_bib35","doi-asserted-by":"crossref","first-page":"478","DOI":"10.1109\/TCAD.2018.2889756","article-title":"Optimal generalized H-tree topology and buffering for high-performance and low-power clock distribution","volume":"39","author":"Han","year":"2018","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"issue":"5","key":"10.1016\/j.vlsi.2026.102665_bib36","doi-asserted-by":"crossref","first-page":"249","DOI":"10.3390\/a18050249","article-title":"A method for synthesizing ultra-large-scale clock trees","volume":"18","author":"Li","year":"2025","journal-title":"Algorithms"},{"issue":"2","key":"10.1016\/j.vlsi.2026.102665_bib38","doi-asserted-by":"crossref","first-page":"478","DOI":"10.1109\/TCAD.2018.2889756","article-title":"Optimal generalized H-tree topology and buffering for high-performance and low-power clock distribution","volume":"39","author":"Han","year":"2018","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"key":"10.1016\/j.vlsi.2026.102665_bib39","series-title":"Proceedings of the 61st ACM\/IEEE Design Automation Conference","first-page":"1","article-title":"Toward controllable hierarchical clock tree synthesis with skew-latency-load tree","author":"Li","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib40","series-title":"International Workshop on Power and Timing Modeling, Optimization and Simulation","first-page":"511","article-title":"A practical ASIC methodology for flexible clock tree synthesis with routing blockages","author":"Wang","year":"2003"},{"key":"10.1016\/j.vlsi.2026.102665_bib41","series-title":"2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)","first-page":"1","article-title":"An enhanced clock tree synthesis methodology for optimizing power in physical design","author":"Anirudh","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib37","series-title":"Best Practices for Floorplanning and Placement to Meet Timing Closure in mm-scale Soc Designs","author":"Marvellous","year":"2025"},{"key":"10.1016\/j.vlsi.2026.102665_bib42","series-title":"Proceedings of the 2024 ACM\/IEEE International Symposium on Machine Learning for CAD","first-page":"1","article-title":"Flip-Flop Centric incremental placement for simultaneous timing and clock network power optimization","author":"Roman-Vicharra","year":"2024"},{"issue":"1","key":"10.1016\/j.vlsi.2026.102665_bib43","doi-asserted-by":"crossref","first-page":"131","DOI":"10.1007\/s10470-023-02226-z","article-title":"Power reduction using Unified techniques in Switch-tail Ring counter for sequential circuits","volume":"119","author":"[Angel Prabha","year":"2024","journal-title":"Analog Integr. Circuits Signal Process."},{"issue":"2","key":"10.1016\/j.vlsi.2026.102665_bib44","doi-asserted-by":"crossref","first-page":"280","DOI":"10.1109\/TCAD.2014.2376988","article-title":"Clock-tree aware multibit flip-flop generation during placement for power optimization","volume":"34","author":"Lin","year":"2014","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"issue":"11","key":"10.1016\/j.vlsi.2026.102665_bib45","doi-asserted-by":"crossref","first-page":"2094","DOI":"10.1109\/TVLSI.2011.2168834","article-title":"Fast power-and slew-aware gated clock tree synthesis","volume":"20","author":"Lu","year":"2011","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"10.1016\/j.vlsi.2026.102665_bib46","series-title":"2021 IEEE\/ACS 18th International Conference on Computer Systems and Applications (AICCSA)","first-page":"1","article-title":"A new MBFF merging strategy for post-placement power optimization of IoT devices","author":"Attaoui","year":"2021"},{"key":"10.1016\/j.vlsi.2026.102665_bib47","doi-asserted-by":"crossref","first-page":"218","DOI":"10.54097\/qed5f182","article-title":"Advancements in low-power technologies: Clock-Gated circuits and beyond","volume":"81","author":"Hu","year":"2024","journal-title":"Highlights Sci. Eng. Technol"},{"key":"10.1016\/j.vlsi.2026.102665_bib48","series-title":"2016 IEEE International Symposium on Circuits and Systems (ISCAS)","first-page":"2591","article-title":"Top-level activity-driven clock tree synthesis with clock skew variation considered","author":"Wang","year":"2016"},{"issue":"4","key":"10.1016\/j.vlsi.2026.102665_bib49","doi-asserted-by":"crossref","first-page":"382","DOI":"10.1016\/j.vlsi.2012.12.001","article-title":"Timing\u2013driven variation\u2013aware synthesis of hybrid mesh\/tree clock distribution networks","volume":"46","author":"Abdelhadi","year":"2013","journal-title":"Integration"},{"key":"10.1016\/j.vlsi.2026.102665_bib50","doi-asserted-by":"crossref","first-page":"177781","DOI":"10.1109\/ACCESS.2024.3506059","article-title":"The impact of asymmetric transistor aging on clock tree design considerations","volume":"12","author":"Ramadan","year":"2024","journal-title":"IEEE Access"},{"issue":"5","key":"10.1016\/j.vlsi.2026.102665_bib51","doi-asserted-by":"crossref","first-page":"424","DOI":"10.5573\/JSTS.2024.24.5.424","article-title":"BTI tolerant clock tree synthesis using LP-based supply voltage alignment","volume":"24","author":"Choi","year":"2024","journal-title":"Journal of semiconductor technology and science"},{"issue":"4","key":"10.1016\/j.vlsi.2026.102665_bib52","doi-asserted-by":"crossref","first-page":"39","DOI":"10.3390\/chips4040039","article-title":"A comprehensive methodology for Soft Error Rate (SER) reduction in clock distribution network","volume":"4","author":"Saenz-Noval","year":"2025","journal-title":"CHIPS"},{"key":"10.1016\/j.vlsi.2026.102665_bib53","series-title":"2021 International Conference on Circuits, Controls and Communications (CCUBE)","first-page":"1","article-title":"Physical design and implementation of Lakshya-Sub-system of built in self Test System","author":"Madhavan","year":"2021"},{"key":"10.1016\/j.vlsi.2026.102665_bib54","series-title":"Proceedings of the 15th IEEE\/ACM International Symposium on networks-on-chip","first-page":"61","article-title":"Synthesis of predictable global NoC by abutment in synchoros VLSI design","author":"Gonz\u00e1lez","year":"2021"},{"key":"10.1016\/j.vlsi.2026.102665_bib55","article-title":"An integrated approach towards VLSI implementation of SFQ logic using standard cell Library and commercial tool suite","volume":"vol.2776","author":"Meher","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib56","doi-asserted-by":"crossref","DOI":"10.1016\/j.vlsi.2024.102261","article-title":"Clock mesh synthesis through dynamic programming with physical parameters consideration","volume":"100","author":"Li","year":"2025","journal-title":"Integration"},{"key":"10.1016\/j.vlsi.2026.102665_bib57","series-title":"2022 IFIP\/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)","first-page":"1","article-title":"Confidential inference in decision trees: FPGA design and implementation","author":"Karn","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib58","series-title":"2023 International Conference on Circuit Power and Computing Technologies (ICCPCT)","first-page":"138","article-title":"Physical design implementation and measurement of timing metrics of 32-Bit LEON SPARC processor used in space applications","author":"Rangeetha","year":"2023"},{"key":"10.1016\/j.vlsi.2026.102665_bib59","series-title":"2024 IEEE International Symposium on Smart Electronic Systems (Ises)","first-page":"368","article-title":"Power, performance and area optimization of asynchronous FIFO","author":"Porel","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib60","series-title":"2024 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","first-page":"153","article-title":"Power optimization techniques during synthesis and physical design for a low-power RISC-V design","author":"Gowda","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib61","series-title":"2021 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)","first-page":"1","article-title":"Rtl to gdsii of harvard structure risc processor","author":"Aradhya","year":"2021"},{"key":"10.1016\/j.vlsi.2026.102665_bib62","article-title":"Benchmarking end-to-end performance of ai-based chip placement algorithms","author":"Wang","year":"2024","journal-title":"arXiv preprint arXiv:2407.15026"},{"issue":"20","key":"10.1016\/j.vlsi.2026.102665_bib63","doi-asserted-by":"crossref","first-page":"4340","DOI":"10.3390\/electronics12204340","article-title":"Shallow clock tree pre-estimation for designing clock tree synthesizable verilog RTLs","volume":"12","author":"Kwon","year":"2023","journal-title":"Electronics"},{"key":"10.1016\/j.vlsi.2026.102665_bib64","series-title":"Design, Automation & Test in Europe Conference & Exhibition (DATE)","first-page":"1504","article-title":"Clock data compensation aware clock tree synthesis in digital circuits with adaptive clock generation","author":"Na","year":"2017"},{"key":"10.1016\/j.vlsi.2026.102665_bib65","series-title":"Proceedings of the 50th Annual Design Automation Conference","first-page":"1","article-title":"An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem","author":"Kim","year":"2013"},{"issue":"3","key":"10.1016\/j.vlsi.2026.102665_bib66","doi-asserted-by":"crossref","first-page":"523","DOI":"10.1109\/TVLSI.2011.2104982","article-title":"Flexible and reconfigurable mismatch-tolerant serial clock distribution networks","volume":"20","author":"Chattopadhyay","year":"2011","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"10.1016\/j.vlsi.2026.102665_bib67","series-title":"Proceedings of the 2020 on Great Lakes Symposium on VLSI","first-page":"399","article-title":"Zero-skew clock network synthesis for monolithic 3d ics with minimum wirelength","author":"Wang","year":"2020"},{"issue":"4","key":"10.1016\/j.vlsi.2026.102665_bib68","first-page":"1","article-title":"Clock tree synthesis for TSV-based 3D IC designs","volume":"16","author":"Kim","year":"2011","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"issue":"3","key":"10.1016\/j.vlsi.2026.102665_bib69","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3313798","article-title":"Thermal-aware 3D symmetrical buffered clock tree synthesis","volume":"24","author":"Oh","year":"2019","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"10.1016\/j.vlsi.2026.102665_bib70","series-title":"2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","first-page":"1","article-title":"Ternary clock tree synthesis for 3D ICs","author":"Pavlidis","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib71","series-title":"Proceedings of the Great Lakes Symposium on VLSI 2025","first-page":"619","article-title":"Inductance-aware clock network synthesis considering hierarchical interconnects in 3D ICs","author":"Zhou","year":"2025"},{"key":"10.1016\/j.vlsi.2026.102665_bib72","series-title":"2013 IEEE International Symposium on Circuits and Systems (ISCAS)","first-page":"2654","article-title":"Synthesis of 3D clock tree with pre-bond testability","author":"Wang","year":"2013"},{"key":"10.1016\/j.vlsi.2026.102665_bib73","series-title":"2016 IFIP\/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)","first-page":"1","article-title":"Power-efficient and slew-aware three dimensional gated clock tree synthesis","author":"Lin","year":"2016"},{"key":"10.1016\/j.vlsi.2026.102665_bib74","series-title":"Proceedings of the 39th International Conference on Computer-Aided Design","first-page":"1","article-title":"Pin-3D: a physical synthesis and post-layout optimization flow for heterogeneous monolithic 3D ICs","author":"Pentapati","year":"2020"},{"key":"10.1016\/j.vlsi.2026.102665_bib75","series-title":"2020 IEEE VLSI DEVICE CIRCUIT AND SYSTEM (VLSI DCS)","first-page":"468","article-title":"Design of low power & high performance multi source H-tree clock distribution network","author":"Srivatsa","year":"2020"},{"key":"10.1016\/j.vlsi.2026.102665_bib76","article-title":"A systematic approach for multi-objective double-side clock tree synthesis","author":"Jiang","year":"2025","journal-title":"arXiv preprint arXiv:2503.12512"},{"key":"10.1016\/j.vlsi.2026.102665_bib77","series-title":"Proceedings of the 30th Asia and South Pacific Design Automation Conference","first-page":"294","article-title":"Toward advancing 3D-ICs physical design: challenges and opportunities","author":"Zhao","year":"2025"},{"key":"10.1016\/j.vlsi.2026.102665_bib78","unstructured":"Madhuri, G. M. G., and J. Selvakumar. \"Machine-Learning Techniques for Predicting Post-CTS Worst Negative Slack.\"."},{"key":"10.1016\/j.vlsi.2026.102665_bib79","series-title":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","first-page":"1","article-title":"Transient clock power estimation of pre-CTS netlist","author":"Kwon","year":"2018"},{"key":"10.1016\/j.vlsi.2026.102665_bib80","series-title":"Proceedings of the 2022 ACM\/IEEE Workshop on Machine Learning for CAD","first-page":"7","article-title":"From global route to detailed route: ML for fast and accurate wire parasitics and timing prediction","author":"Chhabria","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib82","series-title":"Proceedings of the 2024 International Symposium on Physical Design","first-page":"115","article-title":"DSO. ai-A distributed System to optimize physical design flows","author":"Verma","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib83","doi-asserted-by":"crossref","first-page":"87869","DOI":"10.1109\/ACCESS.2023.3304534","article-title":"Advanced reinforcement learning solution for clock skew engineering: modified Q-table update technique for peak current and IR drop minimization","volume":"11","author":"Beheshti-Shirazi","year":"2023","journal-title":"IEEE Access"},{"key":"10.1016\/j.vlsi.2026.102665_bib84","series-title":"Proceedings of the 2024 International Symposium on Physical Design","first-page":"71","article-title":"Challenges in floorplanning and macro placement for modern SoCs","author":"Tseng","year":"2024"},{"issue":"9","key":"10.1016\/j.vlsi.2026.102665_bib85","doi-asserted-by":"crossref","first-page":"3104","DOI":"10.1109\/TCAD.2021.3122109","article-title":"A clock tree prediction and optimization framework using generative adversarial learning","volume":"41","author":"Lu","year":"2021","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"key":"10.1016\/j.vlsi.2026.102665_bib86","series-title":"2022 IEEE 35th International system-on-chip Conference (SOCC)","first-page":"1","article-title":"Machine learning based parameter tuning for performance and power optimization of multisource clock tree synthesis","author":"Ray","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib81","doi-asserted-by":"crossref","first-page":"101","DOI":"10.54254\/2755-2721\/2025.22281","article-title":"Graph neural networks for efficient clock tree synthesis optimization in complex SoC designs","volume":"150","author":"Wu","year":"2025","journal-title":"Applied and Computational Engineering"},{"issue":"12","key":"10.1016\/j.vlsi.2026.102665_bib87","doi-asserted-by":"crossref","first-page":"227401","DOI":"10.1007\/s11432-022-3571-8","article-title":"CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA)","volume":"65","author":"Chai","year":"2022","journal-title":"Sci China Inf Sci"},{"key":"10.1016\/j.vlsi.2026.102665_bib88","series-title":"2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD)","first-page":"1","article-title":"Circuitops: an ml infrastructure enabling generative ai for VLSI circuit optimization","author":"Liang","year":"2023"},{"key":"10.1016\/j.vlsi.2026.102665_bib89","article-title":"AiEDA: an open-source AI-Aided Design Library for design-to-vector","author":"Qiu","year":"2025","journal-title":"arXiv preprint arXiv:2511.05823"},{"key":"10.1016\/j.vlsi.2026.102665_bib90","series-title":"Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design","first-page":"1","article-title":"OCTS: an optical clock tree synthesis methodology for 2.5 D systems","author":"Tsekouras","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib91","series-title":"2022 2nd International Conference on Electrical Engineering and Mechatronics Technology (ICEEMT)","first-page":"249","article-title":"A clock tree synthesis scheme based on flexible H-tree","author":"Wang","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib92","series-title":"2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","first-page":"1","article-title":"A fast security closure approach for EM-based attacks on general multi-segment interconnects","author":"Stoikos","year":"2024"},{"issue":"5","key":"10.1016\/j.vlsi.2026.102665_bib93","first-page":"1","article-title":"A novel clock tree aware placement methodology for single flux quantum logic circuits with maximum path length consideration","volume":"32","author":"Wang","year":"2022","journal-title":"IEEE Trans. Appl. Supercond."},{"key":"10.1016\/j.vlsi.2026.102665_bib94","series-title":"2024 IEEE International Students' Conference on Electrical, Electronics and Computer Science (SCEECS)","first-page":"1","article-title":"A technique to optimize clock latency after CCOpt exploiting useful skew","author":"Dhar","year":"2024"},{"issue":"5","key":"10.1016\/j.vlsi.2026.102665_bib95","doi-asserted-by":"crossref","first-page":"1481","DOI":"10.1109\/TCAD.2021.3079126","article-title":"Algorithm selection framework for legalization using deep convolutional neural networks and transfer learning","volume":"41","author":"Netto","year":"2021","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"key":"10.1016\/j.vlsi.2026.102665_bib96","series-title":"2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA)","first-page":"1","article-title":"An enhanced clock tree synthesis methodology for optimizing power in physical design","author":"Anirudh","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib97","doi-asserted-by":"crossref","DOI":"10.1016\/j.micpro.2023.104913","article-title":"Clock tree generation by abutment in synchoros VLSI design","volume":"102","author":"Stathis","year":"2023","journal-title":"Microprocess. Microsyst."},{"key":"10.1016\/j.vlsi.2026.102665_bib98","series-title":"2024 Global Conference on Communications and Information Technologies (GCCIT)","first-page":"1","article-title":"Design of clock tree distributor with systematic scheduler for stability","author":"Arunkumar","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib99","series-title":"2020 IEEE International Symposium on Smart Electronic Systems (Ises)(Formerly Inis)","first-page":"312","article-title":"Designing of an optimization technique for the prediction of CTS outcomes using neural network","author":"Nagaria","year":"2020"},{"key":"10.1016\/j.vlsi.2026.102665_bib100","series-title":"2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID)","first-page":"80","article-title":"Automated debugger for optimum physical clock structure targeting minimal latency","author":"Shah","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib101","series-title":"2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS)","first-page":"1","article-title":"Hybrid multisource clock tree synthesis","author":"Chong","year":"2021"},{"key":"10.1016\/j.vlsi.2026.102665_bib102","series-title":"2022 23rd International Symposium on Quality Electronic Design (ISQED)","first-page":"1","article-title":"Path-based pre-routing timing prediction for modern very large-scale integration designs","author":"Chen","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib103","series-title":"2024 IEEE Physical Assurance and Inspection of Electronics (PAINE)","first-page":"1","article-title":"Isolation Forest based TinyML for detecting hardware trojans on FPGA in real time","author":"Gurram","year":"2024"},{"key":"10.1016\/j.vlsi.2026.102665_bib104","series-title":"Proceedings of the 2022 ACM\/IEEE Workshop on Machine Learning for CAD","first-page":"127","article-title":"Graph representation learning for gate arrival time prediction","author":"Shrestha","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib105","series-title":"2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID)","first-page":"80","article-title":"Automated debugger for optimum physical clock structure targeting minimal latency","author":"Shah","year":"2022"},{"key":"10.1016\/j.vlsi.2026.102665_bib106","series-title":"2023 Second International Conference on Trends in Electrical, Electronics, and Computer Engineering (TEECCON)","first-page":"293","article-title":"Implementation of Routing-denser PnR flow for an efficient IC block level design","author":"Jenila","year":"2023"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926026000209?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926026000209?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T09:30:59Z","timestamp":1773221459000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0167926026000209"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5]]},"references-count":106,"alternative-id":["S0167926026000209"],"URL":"https:\/\/doi.org\/10.1016\/j.vlsi.2026.102665","relation":{},"ISSN":["0167-9260"],"issn-type":[{"value":"0167-9260","type":"print"}],"subject":[],"published":{"date-parts":[[2026,5]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Clock tree synthesis in modern VLSI: From foundational algorithms to AI-driven optimization","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.vlsi.2026.102665","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Elsevier B.V. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}],"article-number":"102665"}}