{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T17:59:16Z","timestamp":1781632756920,"version":"3.54.5"},"reference-count":37,"publisher":"Elsevier BV","license":[{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-017"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-012"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-004"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61804037"],"award-info":[{"award-number":["61804037"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[2026,7]]},"DOI":"10.1016\/j.vlsi.2026.102727","type":"journal-article","created":{"date-parts":[[2026,4,10]],"date-time":"2026-04-10T00:59:08Z","timestamp":1775782748000},"page":"102727","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"special_numbering":"C","title":["An effective test-per-clock test scheme based on dynamically-partitioned reconfigurable scan chains"],"prefix":"10.1016","volume":"109","author":[{"given":"Tieqiao","family":"Liu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chao","family":"Qian","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yijun","family":"Song","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"78","reference":[{"key":"10.1016\/j.vlsi.2026.102727_bib1","series-title":"Proc. of 15th VLSI Test Symposium","first-page":"459","article-title":"An experimental study comparing the relative effectiveness of functional, scan, IDDQ, and delay fault testing","author":"Nigh","year":"1997"},{"key":"10.1016\/j.vlsi.2026.102727_bib2","series-title":"2024 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), Mangalore, India","article-title":"Improved scan chain stitching for reducing test power","author":"Annamareddy","year":"2024"},{"issue":"8","key":"10.1016\/j.vlsi.2026.102727_bib3","doi-asserted-by":"crossref","DOI":"10.1587\/elex.15.20180144","article-title":"An efficient controlled LFSR hybrid BIST scheme","volume":"15","author":"Liu","year":"2018","journal-title":"IEICE Electron. Express"},{"key":"10.1016\/j.vlsi.2026.102727_bib4","series-title":"Proc of Digest of Papers of 1979 Test Conference. Philadelphia","first-page":"37","article-title":"Built in logic block observation techniques","author":"Konemann","year":"1979"},{"key":"10.1016\/j.vlsi.2026.102727_bib5","series-title":"Proc of International Symposium on Circuits and Systems. San Jose","first-page":"1054","article-title":"Concurrent Built-In logic block observer (CBILBO)","author":"Wang","year":"1986"},{"issue":"6","key":"10.1016\/j.vlsi.2026.102727_bib6","doi-asserted-by":"crossref","first-page":"1090","DOI":"10.1109\/TVLSI.2010.2043452","article-title":"An accumulator\u2014based test-per-clock scheme","volume":"19","author":"Magos","year":"2011","journal-title":"IEEE Transactions on Very Large Scale Integration:vlsi"},{"key":"10.1016\/j.vlsi.2026.102727_bib7","series-title":"Instrumentation and Measurement, Computer, Communication and Control (IMCCC), 2014 Fourth International Conference on","first-page":"505","article-title":"A low power test-per-clock BIST scheme through selectively activating multi two-bit TRCs","author":"Zhou","year":"2014"},{"key":"10.1016\/j.vlsi.2026.102727_bib8","series-title":"Proc of 2012 International Conference on Image Analysis and Signal Processing, Huangzhou, China","first-page":"1","article-title":"A low power testing architecture for test-per-clock BIST","author":"Haijun","year":"2012"},{"issue":"3","key":"10.1016\/j.vlsi.2026.102727_bib9","doi-asserted-by":"crossref","first-page":"651","DOI":"10.1109\/TIM.2007.911707","article-title":"Structure design and optimization of 2-D LFSR-based multisequence test generator in Built-In self-test","volume":"57","author":"Zhang","year":"2008","journal-title":"IEEE Trans. Instrum. Meas."},{"key":"10.1016\/j.vlsi.2026.102727_bib10","series-title":"Simultaneous self-testing System: USA, US4513418","author":"Bardell","year":"1985"},{"issue":"1","key":"10.1016\/j.vlsi.2026.102727_bib11","first-page":"9","article-title":"E-BIST: enhanced test-per-clock BIST architecture. Computers and digital techniques","volume":"149","author":"Son","year":"2002","journal-title":"IEE Proceedings -"},{"issue":"10","key":"10.1016\/j.vlsi.2026.102727_bib12","doi-asserted-by":"crossref","first-page":"672","DOI":"10.1587\/elex.7.672","article-title":"A low cost test pattern generator for test-per-clock BIST scheme","volume":"7","author":"Lei","year":"2010","journal-title":"IEICE Electron. Express"},{"key":"10.1016\/j.vlsi.2026.102727_bib13","series-title":"2020 IEEE 29th Asian Test Symposium (ATS), Penang, Malaysia","first-page":"1","article-title":"A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applications","author":"Alamgir","year":"2020"},{"issue":"1","key":"10.1016\/j.vlsi.2026.102727_bib14","first-page":"46","article-title":"Circular self-test path: a low-cost BIST technique. computer-aided design of integrated circuits and systems","volume":"8","author":"Krasniewski","year":"1987","journal-title":"IEEE Transactions on"},{"issue":"S1","key":"10.1016\/j.vlsi.2026.102727_bib15","doi-asserted-by":"crossref","first-page":"20","DOI":"10.1016\/S1007-0214(07)70078-0","article-title":"Deterministic circular self test path","volume":"12","author":"Wen","year":"2007","journal-title":"J. Tsinghua Univ. (Sci. Technol.)"},{"issue":"3","key":"10.1016\/j.vlsi.2026.102727_bib16","first-page":"13","article-title":"BIST structure and test vector generation based on a controlled LFSR","volume":"7","author":"Chen","year":"2002","journal-title":"Journal of Circuits and Systems"},{"key":"10.1016\/j.vlsi.2026.102727_bib17","series-title":"Proc of 7th IEEE International On-Line Testing Workshop","first-page":"90","article-title":"Test-per-Clock testing of the circuits with scan","author":"Novak","year":"2001"},{"issue":"1","key":"10.1016\/j.vlsi.2026.102727_bib18","doi-asserted-by":"crossref","first-page":"109","DOI":"10.1023\/B:JETT.0000009317.31947.c8","article-title":"Test-per-clock logic BIST with semi-deterministic test patterns and zero-aliasing compactor","volume":"20","author":"Nov\u00e1k","year":"2004","journal-title":"J. Electron. Test."},{"issue":"5","key":"10.1016\/j.vlsi.2026.102727_bib19","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/MAES.2014.130192","article-title":"An effective deterministic test generation for test-per-clock testing","volume":"29","author":"Liu","year":"2014","journal-title":"IEEE Aero. Electron. Syst. Mag."},{"key":"10.1016\/j.vlsi.2026.102727_bib20","series-title":"A test-per-cycle BIST Architecture with Low Area Overhead and No Storage Requirement. 2016 International Symposium on VLSI Design","first-page":"1","author":"Shiao","year":"2016"},{"issue":"6","key":"10.1016\/j.vlsi.2026.102727_bib21","doi-asserted-by":"crossref","first-page":"1028","DOI":"10.1109\/TCAD.2018.2834441","article-title":"Logic BIST with capture-per-clock hybrid test points","volume":"38","author":"Moghaddam","year":"2019","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"issue":"1","key":"10.1016\/j.vlsi.2026.102727_bib22","doi-asserted-by":"crossref","first-page":"76","DOI":"10.1109\/TVLSI.2020.3025138","article-title":"Time and area optimized testing of automotive ics","volume":"29","author":"Mukherjee","year":"2021","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"10.1016\/j.vlsi.2026.102727_bib23","doi-asserted-by":"crossref","first-page":"249","DOI":"10.1016\/j.microrel.2017.10.016","article-title":"Test response compaction method with improved detection and diagnostic abilities","volume":"80","author":"Novak","year":"2018","journal-title":"Microelectron. Reliab."},{"issue":"2","key":"10.1016\/j.vlsi.2026.102727_bib24","doi-asserted-by":"crossref","first-page":"298","DOI":"10.1109\/TCAD.2008.2009159","article-title":"Dynamic scan chain partitioning for reducing peak shift power during test","volume":"28","author":"Almukhaizim","year":"2009","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"issue":"6","key":"10.1016\/j.vlsi.2026.102727_bib25","doi-asserted-by":"crossref","first-page":"999","DOI":"10.1109\/TCAD.2008.923260","article-title":"A reconfigurable scan architecture with weighted scan-enable signals for deterministic BIST","volume":"27","author":"Xiang","year":"2008","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"key":"10.1016\/j.vlsi.2026.102727_bib26","series-title":"Test-Per-Clock Based on dynamically-partitioned Reconfigurable Scan Chains","author":"Rajski","year":"2016"},{"key":"10.1016\/j.vlsi.2026.102727_bib27","series-title":"Test-Per-Clock Based on Dynamically Partitioned Reconfigurable Scan Chains","author":"Rajski","year":"2017"},{"key":"10.1016\/j.vlsi.2026.102727_bib28","series-title":"Proc of IEEE International Test Conference","first-page":"1","article-title":"Launch-on-Shift-Capture transition tests","author":"Park","year":"2008"},{"key":"10.1016\/j.vlsi.2026.102727_bib29","series-title":"2021 12th International Conference on Computing Communication and Networking Technologies (ICCCNT), Kharagpur, India","first-page":"1","article-title":"Heuristics for the generalized graph coloring problem","author":"Kare","year":"2021"},{"key":"10.1016\/j.vlsi.2026.102727_bib30","series-title":"Atalanta: an Efficient ATPG for Combinational Circuits. Technical Report","author":"Lee","year":"1993"},{"issue":"9","key":"10.1016\/j.vlsi.2026.102727_bib31","doi-asserted-by":"crossref","first-page":"1048","DOI":"10.1109\/43.536711","article-title":"HOPE: an efficient parallel fault simulator for synchronous sequential circuits","volume":"15","author":"Lee","year":"1996","journal-title":"Journal of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"11","key":"10.1016\/j.vlsi.2026.102727_bib32","doi-asserted-by":"crossref","first-page":"1361","DOI":"10.1109\/12.247839","article-title":"An efficient algorithm for sequential circuit test generation","volume":"42","author":"Kelsey","year":"1993","journal-title":"IEEE Trans. Comput."},{"issue":"2","key":"10.1016\/j.vlsi.2026.102727_bib33","doi-asserted-by":"crossref","first-page":"103","DOI":"10.1016\/j.vlsi.2010.11.004","article-title":"Test data compression using alternating variable run-length code","volume":"44","author":"Ye","year":"2011","journal-title":"Integration"},{"key":"10.1016\/j.vlsi.2026.102727_bib34","series-title":"Proceedings of 16th European Test Symposium (ETS)","first-page":"204","article-title":"Viterbi-based efficient test data compression","author":"Lee","year":"2011"},{"issue":"1","key":"10.1016\/j.vlsi.2026.102727_bib35","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1007\/s10836-014-5503-3","article-title":"Harzard-based ATPG for improving delay test quality","volume":"31","author":"Liu","year":"2015","journal-title":"J. Electron. Test."},{"issue":"7","key":"10.1016\/j.vlsi.2026.102727_bib36","doi-asserted-by":"crossref","first-page":"859","DOI":"10.1109\/TCAD.2002.1013898","article-title":"Nikolos. A new built-in TPG method for circuits with random pattern resistant faults","volume":"21","author":"Kavousianos","year":"2002","journal-title":"IEEE Trans. Comput. Aided Des. Integrated Circ. Syst."},{"key":"10.1016\/j.vlsi.2026.102727_bib37","series-title":"Proceeding(S) of VLSI Design, 2007. Held Jointly with 6th International Conference on Embedded Systems, 20th International Conference","first-page":"492","article-title":"A reduced complexity algorithm for minimizing N-Detect tests","author":"Kalyana","year":"2007"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926026000829?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926026000829?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2026,6,16]],"date-time":"2026-06-16T17:29:27Z","timestamp":1781630967000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0167926026000829"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,7]]},"references-count":37,"alternative-id":["S0167926026000829"],"URL":"https:\/\/doi.org\/10.1016\/j.vlsi.2026.102727","relation":{},"ISSN":["0167-9260"],"issn-type":[{"value":"0167-9260","type":"print"}],"subject":[],"published":{"date-parts":[[2026,7]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"An effective test-per-clock test scheme based on dynamically-partitioned reconfigurable scan chains","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/j.vlsi.2026.102727","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"\u00a9 2026 Elsevier B.V. All rights are reserved, including those for text and data mining, AI training, and similar technologies.","name":"copyright","label":"Copyright"}],"article-number":"102727"}}