{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,30]],"date-time":"2022-03-30T00:04:09Z","timestamp":1648598649342},"reference-count":5,"publisher":"Elsevier BV","issue":"5","license":[{"start":{"date-parts":[[1973,10,1]],"date-time":"1973-10-01T00:00:00Z","timestamp":118281600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2013,7,17]],"date-time":"2013-07-17T00:00:00Z","timestamp":1374019200000},"content-version":"vor","delay-in-days":14534,"URL":"https:\/\/www.elsevier.com\/open-access\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Computer and System Sciences"],"published-print":{"date-parts":[[1973,10]]},"DOI":"10.1016\/s0022-0000(73)80007-8","type":"journal-article","created":{"date-parts":[[2010,11,10]],"date-time":"2010-11-10T04:46:40Z","timestamp":1289364400000},"page":"522-542","source":"Crossref","is-referenced-by-count":6,"title":["State assignment for realizing modular input-free sequential logical networks without invertors"],"prefix":"10.1016","volume":"7","author":[{"given":"Svetlana P.","family":"Kartashev","sequence":"first","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S0022-0000(73)80007-8_bib1","doi-asserted-by":"crossref","first-page":"54","DOI":"10.1109\/TC.1970.5008900","article-title":"Iteratively Realized Sequential Circuits","volume":"C-19","author":"Arnold","year":"1970","journal-title":"IEEE Trans. Computers"},{"key":"10.1016\/S0022-0000(73)80007-8_bib2","doi-asserted-by":"crossref","first-page":"697","DOI":"10.1109\/TC.1968.227421","article-title":"A synthesis Technique for Binary Input\/Output Synchronous Sequential Moore Machines","volume":"C-17","author":"Newborn","year":"1968","journal-title":"IEEE Trans. Computers"},{"key":"10.1016\/S0022-0000(73)80007-8_bib3","series-title":"Proc. of the 8th Annual Symposium on Switching and Automata Theory","first-page":"233","article-title":"Modular Decomposition of Synchronous Sequential Machines","author":"Weiner","year":"1967"},{"key":"10.1016\/S0022-0000(73)80007-8_bib4","series-title":"Proceedings of the Symposium on Computers and Automata, P.I.B.","article-title":"Methods for Realizing Sequential Machines on Identical Intergrated Circuits","author":"Kartashev","year":"1971"},{"key":"10.1016\/S0022-0000(73)80007-8_bib5","first-page":"88","article-title":"Rational Assignment Sequential Machines by Means of Canonical Graphs","volume":"6","author":"Kartashev","year":"1967","journal-title":"Izv. Acad. Nauk. SSSR, Tehn. Kibernet."}],"container-title":["Journal of Computer and System Sciences"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0022000073800078?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0022000073800078?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2018,12,6]],"date-time":"2018-12-06T18:52:25Z","timestamp":1544122345000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0022000073800078"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1973,10]]},"references-count":5,"journal-issue":{"issue":"5","published-print":{"date-parts":[[1973,10]]}},"alternative-id":["S0022000073800078"],"URL":"https:\/\/doi.org\/10.1016\/s0022-0000(73)80007-8","relation":{},"ISSN":["0022-0000"],"issn-type":[{"value":"0022-0000","type":"print"}],"subject":[],"published":{"date-parts":[[1973,10]]}}}