{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,4]],"date-time":"2024-12-04T05:31:26Z","timestamp":1733290286536,"version":"3.30.1"},"reference-count":32,"publisher":"Elsevier BV","issue":"11","license":[{"start":{"date-parts":[[2001,11,1]],"date-time":"2001-11-01T00:00:00Z","timestamp":1004572800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microelectronics Reliability"],"published-print":{"date-parts":[[2001,11]]},"DOI":"10.1016\/s0026-2714(01)00030-0","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T14:36:15Z","timestamp":1027607775000},"page":"1739-1749","source":"Crossref","is-referenced-by-count":2,"title":["Novel fully silicided ballasting and MFT design techniques for ESD protection in advanced deep sub-micron CMOS technologies"],"prefix":"10.1016","volume":"41","author":[{"given":"Koen G","family":"Verhaege","sequence":"first","affiliation":[]},{"given":"Christian C","family":"Russ","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S0026-2714(01)00030-0_BIB1","unstructured":"All rights reserved \u2013 Patents Pending"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB2","unstructured":"Palella A, et al. A design methodology for ESD protection networks. EOS\/ESD 1985. p. 24\u201340"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB3","unstructured":"Duvvury C, et al. ESD design considerations for ULSI. EOS\/ESD 1985. p. 45\u20138"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB4","doi-asserted-by":"crossref","unstructured":"Diaz C, et al. Studies of EOS susceptibility in 0.6 \u03bcm nMOS ESD I\/O protection structures. EOS\/ESD 1993. p. 83\u201391","DOI":"10.1016\/0304-3886(94)90035-3"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB5","unstructured":"Diaz C, et al. Source contact placement for efficient ESD\/EOS protection in grounded-substrate MOS IC's. US Patent filed, 1993"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB6","doi-asserted-by":"crossref","unstructured":"Smith JC. An anti-snapback circuit technique for inhibiting parasitic bipolar conduction. EOS\/ESD 1999. p. 62\u20139","DOI":"10.1109\/EOSESD.1999.818991"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB7","doi-asserted-by":"crossref","unstructured":"Krakauer D, et al. ESD protection in a 3.3 V sub-micron silicided CMOS technology. EOS\/ESD 1992. p. 250\u20137","DOI":"10.1016\/0304-3886(93)90004-Q"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB8","first-page":"2","article-title":"ESD failure modes: characteristics, mechanisms and process influences","volume":"TED-39","author":"Amerasekera","year":"1992","journal-title":"IEEE"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB9","unstructured":"Multiple private conversations, including major foundry, major memory and major consumer IC representatives, 1999\/2000"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB10","unstructured":"Amerasekera A, et al. Method for designing shallow junction, salicided NMOS transistors with decreased ESD sensitivity. US Patent number 5,793,083, 11 August, 1998"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB11","doi-asserted-by":"crossref","unstructured":"Chen KL. Effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors. EOS\/ESD 1988. p. 212\u20139","DOI":"10.1109\/16.8788"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB12","unstructured":"Amerasekera A, et al. The impact of technology scaling on ESD robustness and protection circuit design. EOS\/ESD 1994. p. 237\u201345"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB13","doi-asserted-by":"crossref","unstructured":"Amerasekera A, et al. Correlating drain junction scaling, salicided thickness, and lateral NPN behavior with the ESD\/EOS performance of a 0.25 \u03bcm CMOS process. IEDM 1996. p. 893\u20136","DOI":"10.1109\/IEDM.1996.554123"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB14","doi-asserted-by":"crossref","unstructured":"Bock K, et al. Influence of well profile and gate length on ESD performance of a fully silicided 0.25 \u03bcm CMOS technology. EOS\/ESD 1997. p. 308\u201315","DOI":"10.1109\/EOSESD.1997.634258"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB15","doi-asserted-by":"crossref","unstructured":"Amerasekera A, et al. Analysis of snapback behavior on the ESD capability of sub-0.20 \u03bcm NMOS. IRPS 1999. p. 159\u201366","DOI":"10.1109\/RELPHY.1999.761608"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB16","doi-asserted-by":"crossref","unstructured":"Bock K, et al. Influence of gate length on ESD performance for deep sub micron CMOS technology. EOS\/ESD 1999. p. 95\u2013104","DOI":"10.1109\/EOSESD.1999.818995"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB17","doi-asserted-by":"crossref","unstructured":"Maloney T, et al. Novel clamp circuits for IC power supply protection. EOS\/ESD 1995. p. 1\u201312","DOI":"10.1109\/EOSESD.1995.478262"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB18","doi-asserted-by":"crossref","first-page":"1691","DOI":"10.1016\/S0026-2714(98)00172-3","article-title":"Designing power supply clamps for ESD protection of ICs","volume":"38","author":"Maloney","year":"1998","journal-title":"Microelectron Reliab"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB19","doi-asserted-by":"crossref","unstructured":"Maloney T, et al. Stacked PMOS clamps for high voltage power supply protection. EOS\/ESD 1999. p. 70\u20137","DOI":"10.1109\/EOSESD.1999.818992"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB20","doi-asserted-by":"crossref","unstructured":"Notermans G, et al. The effect of silicide on ESD performance. IRPS 1999. p. 154\u20138","DOI":"10.1109\/RELPHY.1999.761607"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB21","unstructured":"Park HB, et al. A novel NMOS transistor for high performance ESD protection devices in 0.18 \u03bcm CMOS technology utilizing salicide process. EOS\/ESD 2000. p. 407\u201312"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB22","unstructured":"Anderson W. Compaq, personal communication, June 2000"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB23","doi-asserted-by":"crossref","unstructured":"Anderson W. ESD protection under bonding pads. EOS\/ESD 1999. p. 88\u201394","DOI":"10.1109\/EOSESD.1999.818994"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB24","unstructured":"Polgreen T, et al. Improving the ESD failure threshold of silicided NMOS output transistors by ensuring uniform current flow. EOS\/ESD 1989. p. 167\u201374"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB25","unstructured":"Krieger G. Non-uniform ESD current distribution due to improper metal routing. EOS\/ESD 1991. p. 104\u20139"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB26","doi-asserted-by":"crossref","unstructured":"Duvvury C, et al. Achieving uniform nMOS device power distribution for sub-micron ESD reliability. IEDM 1992. p. 131\u20134","DOI":"10.1109\/IEDM.1992.307325"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB27","unstructured":"Amerasekera A, Duvvury C. ESD in silicon integrated circuits. Wiley, 1995, ISBN 0 471 95481 0"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB28","unstructured":"Henry LG, et al. TLP calibration, correlation, standards and new techniques. EOS\/ESD 2000. p. 85\u201396"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB29","unstructured":"Mergens M, Verhaege K, Russ C, Armer J, Jozwiak P, Kolluri G, Avery L. Multi-finger turn-on characteristics and design techniques for enhanced ESD performance and width-scaling. EOS\/ESD 2001, in press"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB30","unstructured":"Maloney T, et al. Transmission line pulsing techniques for circuit modeling of ESD phenomena. EOS\/ESD 1985. p. 49\u201354"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB31","unstructured":"Verhaege K. ESREF\/ESD association tutorial on component level ESD testing, Enschede, The Netherlands, 1996"},{"key":"10.1016\/S0026-2714(01)00030-0_BIB32","unstructured":"Henry LG, Verhaege K. EOS\/ESD Symposium TLP tutorial. Anaheim, CA, USA, 2000"}],"container-title":["Microelectronics Reliability"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0026271401000300?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0026271401000300?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2024,12,4]],"date-time":"2024-12-04T03:27:40Z","timestamp":1733282860000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0026271401000300"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2001,11]]},"references-count":32,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2001,11]]}},"alternative-id":["S0026271401000300"],"URL":"https:\/\/doi.org\/10.1016\/s0026-2714(01)00030-0","relation":{},"ISSN":["0026-2714"],"issn-type":[{"type":"print","value":"0026-2714"}],"subject":[],"published":{"date-parts":[[2001,11]]}}}