{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T17:02:11Z","timestamp":1648573331553},"reference-count":17,"publisher":"Elsevier BV","issue":"1","license":[{"start":{"date-parts":[[2002,1,1]],"date-time":"2002-01-01T00:00:00Z","timestamp":1009843200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microelectronics Reliability"],"published-print":{"date-parts":[[2002,1]]},"DOI":"10.1016\/s0026-2714(01)00233-5","type":"journal-article","created":{"date-parts":[[2002,10,14]],"date-time":"2002-10-14T18:58:33Z","timestamp":1034621913000},"page":"15-25","source":"Crossref","is-referenced-by-count":4,"title":["A 0.11 \u03bcm CMOS technology featuring copper and very low k interconnects with high performance and reliability"],"prefix":"10.1016","volume":"42","author":[{"given":"Yoshihiro","family":"Takao","sequence":"first","affiliation":[]},{"given":"Hiroshi","family":"Kudo","sequence":"additional","affiliation":[]},{"given":"Junichi","family":"Mitani","sequence":"additional","affiliation":[]},{"given":"Yoshiyuki","family":"Kotani","sequence":"additional","affiliation":[]},{"given":"Satoshi","family":"Yamaguchi","sequence":"additional","affiliation":[]},{"given":"Keizaburo","family":"Yoshie","sequence":"additional","affiliation":[]},{"given":"Kazuo","family":"Sukegawa","sequence":"additional","affiliation":[]},{"given":"Nobuhisa","family":"Naori","sequence":"additional","affiliation":[]},{"given":"Satoru","family":"Asai","sequence":"additional","affiliation":[]},{"given":"Michiari","family":"Kawano","sequence":"additional","affiliation":[]},{"given":"Takashi","family":"Nagano","sequence":"additional","affiliation":[]},{"given":"Ikuhiro","family":"Yamamura","sequence":"additional","affiliation":[]},{"given":"Masaya","family":"Uematsu","sequence":"additional","affiliation":[]},{"given":"Naoki","family":"Nagashima","sequence":"additional","affiliation":[]},{"given":"Shingo","family":"Kadomura","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S0026-2714(01)00233-5_BIB1","doi-asserted-by":"crossref","first-page":"559","DOI":"10.1109\/IEDM.2000.904381","article-title":"A 0.11 \u03bcm CMOS technology with copper and very low k interconnects for high performance system on a chip cores","author":"Takao","year":"2000","journal-title":"IEDM Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB2","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1109\/VLSIT.1997.623670","article-title":"A 4-\u03bcm2 full-CMOS SRAM cell technology for 0.2-\u03bcm high-performance logic LSIs","author":"Takao","year":"1997","journal-title":"Symp VLSI Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB3","first-page":"131","article-title":"Integration of organic low-k material with Cu-damascene employing novel process","author":"Ikeda","year":"1998","journal-title":"Proc IITC"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB4","first-page":"271","article-title":"Copper dual damascene interconnects with very low-k dielectrics targeting for 130 nm node","author":"Kudo","year":"2000","journal-title":"Proc IITC"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB5","first-page":"667","article-title":"A 0.13-\u03bcm CMOS technology integrating high-speed and low power\/high-density devices with two different well\/channel structures","author":"Imai","year":"1999","journal-title":"IEDM Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB6","first-page":"12","article-title":"A modular 0.13 \u03bcm bulk CMOS foundry technology for high performance and low power applications","author":"Han","year":"2000","journal-title":"Symp VLSI Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB7","first-page":"128","article-title":"A 2 ns access, 500 MHz 288 Kb SRAM macro","author":"Pelella","year":"1996","journal-title":"Symp VLSI Circ Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB8","first-page":"441","article-title":"A novel borderless contact\/interconnect technology using aluminum oxide etch stop for high performance SRAM and logic","author":"Subbanna","year":"1993","journal-title":"IEDM Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB9","first-page":"358","article-title":"A 450 MHz 512 kB second-level cache with a 3.6 GB\/s data bandwidth","volume":"2","author":"Bateman","year":"1998","journal-title":"ISSCC Digest Tech Papers"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB10","first-page":"941","article-title":"A novel embedded SRAM technology with 10-\u03bcm2 full-CMOS cells for 0.25-\u03bcm logic devices","author":"Izawa","year":"1994","journal-title":"IEDM Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB11","first-page":"11","article-title":"A 0.18 \u03bcm CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications","author":"Diaz","year":"1999","journal-title":"Symp VLSI Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB12","first-page":"146","article-title":"A 0.15 \u03bcm CMOS foundry technology with 0.1 \u03bcm devices for high performance applications","author":"Diaz","year":"2000","journal-title":"Symp VLSI Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB13","doi-asserted-by":"crossref","first-page":"563","DOI":"10.1109\/IEDM.2000.904382","article-title":"A 0.13 \u03bcm CMOS technology with 193 nm lithography and Cu\/low-k for high performance applications","author":"Young","year":"2000","journal-title":"IEDM Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB14","first-page":"73","article-title":"The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling","author":"Kimizuka","year":"1999","journal-title":"Symp VLSI Tech Digest"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB15","first-page":"28","article-title":"Reliability and electromigration failure in dual inlaid Cu interconnects","author":"Capasso","year":"2000","journal-title":"Extended Abstracts SSDM"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB16","first-page":"267","article-title":"Scaling effect on electromigration in on-chip Cu wiring","author":"Hu","year":"1999","journal-title":"Proc IITC"},{"key":"10.1016\/S0026-2714(01)00233-5_BIB17","first-page":"101","article-title":"A 0.13 \u03bcm CMOS platform with Cu\/low-k interconnects for system on chip applications","author":"Schiml","year":"2001","journal-title":"Symp VLSI Tech Digest"}],"container-title":["Microelectronics Reliability"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0026271401002335?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0026271401002335?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,5,3]],"date-time":"2019-05-03T03:58:21Z","timestamp":1556855901000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0026271401002335"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,1]]},"references-count":17,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2002,1]]}},"alternative-id":["S0026271401002335"],"URL":"https:\/\/doi.org\/10.1016\/s0026-2714(01)00233-5","relation":{},"ISSN":["0026-2714"],"issn-type":[{"value":"0026-2714","type":"print"}],"subject":[],"published":{"date-parts":[[2002,1]]}}}