{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T13:56:02Z","timestamp":1761486962593,"version":"3.30.2"},"reference-count":14,"publisher":"Elsevier BV","issue":"5","license":[{"start":{"date-parts":[[2003,5,1]],"date-time":"2003-05-01T00:00:00Z","timestamp":1051747200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microelectronics Reliability"],"published-print":{"date-parts":[[2003,5]]},"DOI":"10.1016\/s0026-2714(03)00034-9","type":"journal-article","created":{"date-parts":[[2003,4,30]],"date-time":"2003-04-30T19:34:13Z","timestamp":1051731253000},"page":"685-693","source":"Crossref","is-referenced-by-count":6,"title":["Integrating testability with design space exploration"],"prefix":"10.1016","volume":"43","author":[{"given":"M.","family":"Zwolinski","sequence":"first","affiliation":[]},{"given":"M.S.","family":"Gaur","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S0026-2714(03)00034-9_BIB1","doi-asserted-by":"crossref","first-page":"331","DOI":"10.1023\/A:1012227715327","article-title":"A method for trading off test, area and fault coverage in datapath BIST synthesis","volume":"17","author":"Berthelot","year":"2001","journal-title":"J. Electronic Testing: Theory Appl."},{"key":"10.1016\/S0026-2714(03)00034-9_BIB2","doi-asserted-by":"crossref","first-page":"79","DOI":"10.1023\/A:1008397519162","article-title":"Design for testability techniques at the behavioral and register-transfer levels","volume":"13","author":"Dey","year":"1998","journal-title":"J. Electronic Testing: Theory Appl."},{"key":"10.1016\/S0026-2714(03)00034-9_BIB3","doi-asserted-by":"crossref","unstructured":"Harmanani H, Papachristou C. An improved method for RTL synthesis with testability tradeoffs. In: Proc. International Conference on Computer-Aided Design, 1993. p. 30\u20137","DOI":"10.1109\/ICCAD.1993.580027"},{"key":"10.1016\/S0026-2714(03)00034-9_BIB4","unstructured":"Harmanani H, Saliba R, Khouray M. A genetic algorithm for testable data path synthesis. In: Proc IEEE Canadian Conference on Electrical and Computer Engineering, CCECE, 2001. p. 1073\u20138"},{"key":"10.1016\/S0026-2714(03)00034-9_BIB5","doi-asserted-by":"crossref","unstructured":"Harris IG, Orailoglu A. SYNCBIST: synthesis for concurrent built-in self-testability. In: Proc European Design and Test Conference, 1994. p. 101\u20134","DOI":"10.1109\/ICCD.1994.331864"},{"key":"10.1016\/S0026-2714(03)00034-9_BIB6","doi-asserted-by":"crossref","first-page":"71","DOI":"10.1007\/BF00971941","article-title":"Generating a family of testable designs using the BILBO methodology","volume":"4","author":"Lin","year":"1993","journal-title":"J. Electronic Testing: Theory Appl."},{"key":"10.1016\/S0026-2714(03)00034-9_BIB7","unstructured":"Mohamed AR, Peng Z, Eles P. BIST synthesis: an approach to resource optimization under test time constraints. In: Proc. IEEE International Test Synthesis Workshop, Santa Barbara, USA, March 2001"},{"key":"10.1016\/S0026-2714(03)00034-9_BIB8","doi-asserted-by":"crossref","first-page":"1375","DOI":"10.1109\/43.892861","article-title":"BIST hardware synthesis for RTL data paths based on test compatibility classes","volume":"19","author":"Nicolici","year":"2000","journal-title":"IEEE Trans. Comput. Aided Des."},{"key":"10.1016\/S0026-2714(03)00034-9_BIB9","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1016\/S0167-9260(99)00012-7","article-title":"Unified data path allocation and BIST intrusion","volume":"28","author":"Olcoz","year":"1999","journal-title":"Integration, VLSI J."},{"key":"10.1016\/S0026-2714(03)00034-9_BIB10","doi-asserted-by":"crossref","first-page":"423","DOI":"10.1145\/383251.383253","article-title":"Introducing redundant computation in RTL data paths for reducing BIST resources","volume":"6","author":"Parulkar","year":"2001","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"10.1016\/S0026-2714(03)00034-9_BIB11","doi-asserted-by":"crossref","first-page":"383","DOI":"10.1049\/ip-cdt:20000807","article-title":"Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis","volume":"147","author":"Williams","year":"2000","journal-title":"IEEE Proc. Comput. Digital Tech."},{"key":"10.1016\/S0026-2714(03)00034-9_BIB12","unstructured":"Li X, Masuzawa T, Fujiwara H. Strong self-testability for data paths high-level synthesis. In: Proceedings of the Asian Test Symposium, Taipei, Taiwan, December 2000. p. 229\u201334"},{"key":"10.1016\/S0026-2714(03)00034-9_BIB13","doi-asserted-by":"crossref","unstructured":"Ravi S, Jha NK, Lakshminarayana G. TAO-BIST: a framework for testability analysis and optimisation RTL circuits for BIST. In: Proc IEEE VLSI Test Symposium, 1999. p. 398\u2013406","DOI":"10.1109\/VTEST.1999.766695"},{"year":"2000","series-title":"Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits","author":"Bushnell","key":"10.1016\/S0026-2714(03)00034-9_BIB14"}],"container-title":["Microelectronics Reliability"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0026271403000349?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0026271403000349?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,24]],"date-time":"2019-03-24T00:26:38Z","timestamp":1553387198000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0026271403000349"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,5]]},"references-count":14,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2003,5]]}},"alternative-id":["S0026271403000349"],"URL":"https:\/\/doi.org\/10.1016\/s0026-2714(03)00034-9","relation":{},"ISSN":["0026-2714"],"issn-type":[{"type":"print","value":"0026-2714"}],"subject":[],"published":{"date-parts":[[2003,5]]}}}