{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T23:10:02Z","timestamp":1740870602201,"version":"3.38.0"},"reference-count":95,"publisher":"Elsevier","isbn-type":[{"type":"print","value":"9780123737458"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007]]},"DOI":"10.1016\/s0065-2458(06)69001-3","type":"book-chapter","created":{"date-parts":[[2011,1,19]],"date-time":"2011-01-19T05:56:21Z","timestamp":1295416581000},"page":"1-87","source":"Crossref","is-referenced-by-count":0,"title":["The Architecture of Efficient Multi-Core Processors: A Holistic Approach"],"prefix":"10.1016","author":[{"given":"Rakesh","family":"Kumar","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dean M.","family":"Tullsen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S0065-2458(06)69001-3_bib001","unstructured":"http:\/\/www.amd.com\/us-en\/Processors\/ProductInformation\/0,,30_118_13909,00.html"},{"key":"10.1016\/S0065-2458(06)69001-3_bib002","unstructured":"http:\/\/www.amd.com\/us-en\/processors\/productinformation\/0,,30_118_8825,00.html"},{"key":"10.1016\/S0065-2458(06)69001-3_bib003","unstructured":"http:\/\/www.amd.com\/us-en\/Processors\/ProductInformation\/0,,30_118_9485_9484,00.html"},{"key":"10.1016\/S0065-2458(06)69001-3_bib004","unstructured":"http:\/\/www.arm.com\/products\/cpus\/arm11mpcoremultiprocessor.html"},{"key":"10.1016\/S0065-2458(06)69001-3_bib005","unstructured":"http:\/\/www.broadcom.com\/products\/enterprise-small-office\/communications-processors"},{"key":"10.1016\/S0065-2458(06)69001-3_bib006","unstructured":"http:\/\/www.cavium.com\/octeon_mips64.html"},{"key":"10.1016\/S0065-2458(06)69001-3_bib007","unstructured":"http:\/\/www.geek.com\/procspec\/hp\/pa8800.htm"},{"key":"10.1016\/S0065-2458(06)69001-3_bib008","unstructured":"http:\/\/www.intel.com\/pressroom\/kits\/quickreffam.htm"},{"key":"10.1016\/S0065-2458(06)69001-3_bib009","unstructured":"http:\/\/www.intel.com\/products\/processor\/coreduo\/"},{"key":"10.1016\/S0065-2458(06)69001-3_bib010","unstructured":"http:\/\/www.intel.com\/products\/processor\/pentium_d\/index.htm"},{"key":"10.1016\/S0065-2458(06)69001-3_bib011","unstructured":"http:\/\/www.intel.com\/products\/processor\/pentiumxe\/index.htm"},{"key":"10.1016\/S0065-2458(06)69001-3_bib012","unstructured":"http:\/\/www.intel.com\/products\/processor\/xeon\/index.htm"},{"key":"10.1016\/S0065-2458(06)69001-3_bib013","unstructured":"http:\/\/www.razamicroelectronics.com\/products\/xlr.htm"},{"key":"10.1016\/S0065-2458(06)69001-3_bib014","unstructured":"http:\/\/www.xbox.com\/en-us\/hardware\/xbox360\/powerplay.htm"},{"key":"10.1016\/S0065-2458(06)69001-3_bib015","unstructured":"International Technology Roadmap for Semiconductors 2003, http:\/\/public.itrs.net"},{"year":"1992","series-title":"Alpha 21064 and Alpha 21064A: Hardware Reference Manual","author":"Digital Equipment Corporation","key":"10.1016\/S0065-2458(06)69001-3_bib016"},{"year":"1998","series-title":"Alpha 21164 Microprocessor: Hardware Reference Manual","author":"Digital Equipment Corporation","key":"10.1016\/S0065-2458(06)69001-3_bib017"},{"year":"1998","series-title":"Alpha 21264\/EV6 Microprocessor: Hardware Reference Manual","author":"Compaq Corporation","key":"10.1016\/S0065-2458(06)69001-3_bib018"},{"year":"2002","series-title":"Measuring Processor Performance with SPEC2000\u2014A White Paper","author":"Intel Corporation","key":"10.1016\/S0065-2458(06)69001-3_bib019"},{"key":"10.1016\/S0065-2458(06)69001-3_bib020","doi-asserted-by":"crossref","unstructured":"Annavaram M., Grochowski E., Shen J., \u201cMitigating Amdahl's Law through EPI throttling\u201d, in: International Symposium on Computer Architecture, 2005","DOI":"10.1145\/1080695.1069995"},{"issue":"4","key":"10.1016\/S0065-2458(06)69001-3_bib021","doi-asserted-by":"crossref","first-page":"273","DOI":"10.1145\/6513.6514","article-title":"Cache coherence protocols: Evaluation using a multiprocessor simulation model","volume":"4","author":"Archibald","year":"1986","journal-title":"ACM Trans. Comput. Syst."},{"key":"10.1016\/S0065-2458(06)69001-3_bib022","doi-asserted-by":"crossref","unstructured":"Balakrishnan S., Rajwar R., Upton M., Lai K., \u201cThe impact of performance asymmetry in emerging multicore architectures\u201d, in: International Symposium on Computer Architecture, June 2005","DOI":"10.1145\/1080695.1070012"},{"key":"10.1016\/S0065-2458(06)69001-3_bib023","doi-asserted-by":"crossref","unstructured":"Barroso L., Gharachorloo K., McNamara R., Nowatzyk A., Qadeer S., Sano B., Smith S., Stets R., Verghese B., \u201cPiranha: A scalable architecture based on single-chip multiprocessing\u201d, in: The 27th Annual International Symposium on Computer Architecture, June 2000","DOI":"10.1145\/339647.339696"},{"key":"10.1016\/S0065-2458(06)69001-3_bib024","unstructured":"Bowhill W., \u201cA 300-MHz 64-b quad-issue CMOS microprocessor\u201d, in: ISSCC Digest of Technical Papers, February 1995"},{"key":"10.1016\/S0065-2458(06)69001-3_bib025","doi-asserted-by":"crossref","unstructured":"Brooks D., Tiwari V., Martonosi M., \u201cWattch: A framework for architectural-level power analysis and optimizations\u201d, in: International Symposium on Computer Architecture, June 2000","DOI":"10.1145\/339647.339657"},{"key":"10.1016\/S0065-2458(06)69001-3_bib026","series-title":"The 2001 International Conference on Parallel Architectures and Compilation Techniques","first-page":"211","article-title":"Area and system clock effects on SMT\/CMP processors","author":"Burns","year":"2001"},{"issue":"2","key":"10.1016\/S0065-2458(06)69001-3_bib027","doi-asserted-by":"crossref","DOI":"10.1109\/71.983942","article-title":"SMT layout overhead and scalability","volume":"13","author":"Burns","year":"2002","journal-title":"IEEE Transactions on Parallel and Distributed Systems"},{"key":"10.1016\/S0065-2458(06)69001-3_bib028","doi-asserted-by":"crossref","unstructured":"Clabes J., Friedrich J., Sweet M., DiLullo J., Chu S., Plass D., Dawson J., Muench P., Powell L., Floyd M., Sinharoy B., Lee M., Goulet M., Wagoner J., Schwartz N., Runyon S., Gorman G., Restle P., Kalla R., McGill J., Dodson S., \u201cDesign and implementation of the Power5 microprocessor\u201d, in: International Solid-State Circuits Conference, 2004","DOI":"10.1145\/996566.996749"},{"key":"10.1016\/S0065-2458(06)69001-3_bib029","unstructured":"Collins J., Tullsen D., \u201cClustered multithreaded architectures\u2014pursuing both IPC and cycle time\u201d in: International Parallel and Distributed Processing Symposium, April 2004"},{"issue":"16","key":"10.1016\/S0065-2458(06)69001-3_bib030","article-title":"Compaq chooses SMT for Alpha","volume":"13","author":"Diefendorff","year":"1999","journal-title":"Microprocessor Report"},{"issue":"11","key":"10.1016\/S0065-2458(06)69001-3_bib031","doi-asserted-by":"crossref","DOI":"10.1109\/4.165336","article-title":"A 200-MHz 64-b dual-issue CMOS microprocessor","volume":"27","author":"Dobberpuhl","year":"1992","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"10.1016\/S0065-2458(06)69001-3_bib032","unstructured":"Dolbeau R., Seznec A., \u201cCASH: Revisiting hardware sharing in single-chip parallel processor\u201d, IRISA Report 1491, November 2002"},{"issue":"2","key":"10.1016\/S0065-2458(06)69001-3_bib033","doi-asserted-by":"crossref","DOI":"10.1109\/2.15","article-title":"Synchronization, coherence, and event ordering in multiprocessors","volume":"21","author":"Dubois","year":"1988","journal-title":"IEEE Computer"},{"key":"10.1016\/S0065-2458(06)69001-3_bib034","doi-asserted-by":"crossref","unstructured":"Eickemeyer R.J., Johnson R.E., Kunkel S.R., Squillante M.S., Liu S., \u201cEvaluation of multithreaded uniprocessors for commercial application environments\u201d, in: International Symposium on Computer Architecture, 1996","DOI":"10.1145\/232973.232994"},{"key":"10.1016\/S0065-2458(06)69001-3_bib035","unstructured":"Emer J., \u201cEV8: The post-ultimate Alpha\u201d, in: Conference on Parallel Architectures and Computing Technologies, September 2001"},{"key":"10.1016\/S0065-2458(06)69001-3_bib036","doi-asserted-by":"crossref","unstructured":"Espasa R., Ardanaz F., Emer J., Felix S., Gago J., Gramunt R., Hernandez I., Juan T., Lowney G., Mattina M., Seznec A., \u201cTarantula: A vector extension to the alpha architecture\u201d, in: International Symposium on Computer Architecture, May 2002","DOI":"10.1145\/545214.545247"},{"key":"10.1016\/S0065-2458(06)69001-3_bib037","unstructured":"Frank S.J., \u201cTightly coupled multiprocessor systems speed memory access times\u201d, in: Electron, January 1984"},{"key":"10.1016\/S0065-2458(06)69001-3_bib038","unstructured":"Ghiasi S., Grunwald D., \u201cAide de camp: Asymmetric dual core design for power and energy reduction\u201d, University of Colorado Technical Report CU-CS-964-03, 2003"},{"key":"10.1016\/S0065-2458(06)69001-3_bib039","doi-asserted-by":"crossref","unstructured":"Ghiasi S., Keller T., Rawson F., \u201cScheduling for heterogeneous processors in server systems\u201d, in: Computing Frontiers, 2005","DOI":"10.1145\/1062261.1062295"},{"key":"10.1016\/S0065-2458(06)69001-3_bib040","unstructured":"Gieseke B., \u201cA 600-MHz superscalar RISC microprocessor with out-of-order execution\u201d, in: ISSCC Digest of Technical Papers, February 1997"},{"key":"10.1016\/S0065-2458(06)69001-3_bib041","unstructured":"Grochowski E., Ronen R., Shen J., Wang H., \u201cBest of both latency and throughput\u201d, in: IEEE International Conference on Computer Design, 2004"},{"key":"10.1016\/S0065-2458(06)69001-3_bib042","unstructured":"Gupta S., Keckler S., Burger D., \u201cTechnology independent area and delay estimates for microprocessor building blocks\u201d, University of Texas at Austin Technical Report TR-00-05, 1998"},{"issue":"9","key":"10.1016\/S0065-2458(06)69001-3_bib043","article-title":"A single-chip multiprocessor","volume":"30","author":"Hammond","year":"1997","journal-title":"IEEE Computer"},{"key":"10.1016\/S0065-2458(06)69001-3_bib044","doi-asserted-by":"crossref","unstructured":"Hammond L., Willey M., Olukotun K., \u201cData speculation support for a chip multiprocessor\u201d, in: The Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, October 1998","DOI":"10.1145\/291069.291020"},{"year":"2002","series-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy","key":"10.1016\/S0065-2458(06)69001-3_bib045"},{"issue":"9","key":"10.1016\/S0065-2458(06)69001-3_bib046","doi-asserted-by":"crossref","first-page":"18","DOI":"10.1109\/2.84896","article-title":"Computer technology and architecture: An evolving interaction","volume":"24","author":"Hennessy","year":"1991","journal-title":"Computer"},{"key":"10.1016\/S0065-2458(06)69001-3_bib047","unstructured":"Horowitz M., Alon E., Patil D., Naffziger S., Kumar R., Bernstein K., \u201cScaling, power, and the future of CMOS\u201d, in: IEEE International Electron Devices Meeting, December 2005"},{"key":"10.1016\/S0065-2458(06)69001-3_bib048","unstructured":"Horowitz M., Ho R., Mai K., \u201cThe future of wires\u201d, Invited Workshop Paper for SRC Conference, May 1999"},{"key":"10.1016\/S0065-2458(06)69001-3_bib049","unstructured":"IBM, Power4, http:\/\/www.research.ibm.com\/power4"},{"key":"10.1016\/S0065-2458(06)69001-3_bib050","unstructured":"IBM, \u201cPower5: Presentation at microprocessor forum\u201d, 2003"},{"key":"10.1016\/S0065-2458(06)69001-3_bib051","doi-asserted-by":"crossref","unstructured":"Kaanta C., Cote W., Cronin J., Holland K., Lee P., Wright T., \u201cSubmicron wiring technology with tungsten and planarization\u201d, in: Fifth VLSI Multilevel Interconnection Conference, 1988","DOI":"10.1109\/IEDM.1987.191389"},{"key":"10.1016\/S0065-2458(06)69001-3_bib052","doi-asserted-by":"crossref","DOI":"10.1147\/rd.494.0589","article-title":"Introduction to the Cell multiprocessor","author":"Kahle","year":"2005","journal-title":"IBM Journal of Research and Development"},{"key":"10.1016\/S0065-2458(06)69001-3_bib053","doi-asserted-by":"crossref","unstructured":"Kim C., Burger D., Keckler S., \u201cAn adaptive, non-uniform cache structure for wire-delay dominated on-chip caches\u201d, in: International Conference on Architectural Support for Programming Languages and Operating Systems, 2002","DOI":"10.1145\/605418.605420"},{"key":"10.1016\/S0065-2458(06)69001-3_bib054","unstructured":"Klauser A., \u201cTrends in high-performance microprocessor design\u201d, in: Telematik-2001, 2001"},{"key":"10.1016\/S0065-2458(06)69001-3_bib055","doi-asserted-by":"crossref","unstructured":"Kongetira P., Aingaran K., Olukotun K., \u201cNiagara: A 32-way multithreaded Sparc processor\u201d in: IEEE MICRO Magazine, March 2005","DOI":"10.1109\/MM.2005.35"},{"key":"10.1016\/S0065-2458(06)69001-3_bib056","unstructured":"Kotla R., Devgan A., Ghiasi S., Keller T., Rawson F., \u201cCharacterizing the impact of different memory-intensity levels\u201d, in: IEEE 7th Annual Workshop on Workload Characterization, 2004"},{"key":"10.1016\/S0065-2458(06)69001-3_bib057","unstructured":"Kowaleski J., \u201cImplementation of an Alpha microprocessor in SOI\u201d, in: ISSCC Digest of Technical Papers, February 2003"},{"key":"10.1016\/S0065-2458(06)69001-3_bib058","doi-asserted-by":"crossref","unstructured":"Krishnan V., Torrellas J., \u201cA clustered approach to multithreaded processors\u201d, in: International Parallel Processing Symposium, March 1998, pp. 627\u2013634","DOI":"10.1109\/IPPS.1998.669992"},{"key":"10.1016\/S0065-2458(06)69001-3_bib059","doi-asserted-by":"crossref","unstructured":"Kumar A., \u201cThe HP PA-8000 RISC CPU\u201d, in: Hot Chips VIII, August 1996","DOI":"10.1109\/40.592310"},{"key":"10.1016\/S0065-2458(06)69001-3_bib060","doi-asserted-by":"crossref","unstructured":"Kumar R., Farkas K.I., Jouppi N.P., Ranganathan P., Tullsen D.M., \u201cSingle-ISA heterogeneous multi-core architectures: The potential for processor power reduction\u201d, in: International Symposium on Microarchitecture, December 2003","DOI":"10.1109\/L-CA.2003.6"},{"key":"10.1016\/S0065-2458(06)69001-3_bib061","unstructured":"Kumar R., Jouppi N.P., Tullsen D.M., \u201cConjoined-core chip multiprocessing\u201d, in: International Symposium on Microarchitecture, December 2004"},{"key":"10.1016\/S0065-2458(06)69001-3_bib062","doi-asserted-by":"crossref","unstructured":"Kumar R., Tullsen D.M., Jouppi N.P., \u201cCore architecture optimization for heterogeneous chip multiprocessors\u201d, in: 15th International Symposium on Parallel Architectures and Compilation Techniques, September 2006","DOI":"10.1145\/1152154.1152162"},{"key":"10.1016\/S0065-2458(06)69001-3_bib063","doi-asserted-by":"crossref","unstructured":"Kumar R., Tullsen D.M., Ranganathan P., Jouppi N.P., Farkas K.I., \u201cSingle-ISA heterogeneous multi-core architectures for multithreaded workload performance\u201d, in: International Symposium on Computer Architecture, June 2004","DOI":"10.1109\/ISCA.2004.1310764"},{"key":"10.1016\/S0065-2458(06)69001-3_bib064","doi-asserted-by":"crossref","unstructured":"Kumar R., Zyuban V., Tullsen D.M., \u201cInterconnections in multi-core architectures: Understanding mechanisms, overheads and scaling\u201d, in: Proceedings of International Symposium on Computer Architecture, June 2005","DOI":"10.1145\/1080695.1070004"},{"key":"10.1016\/S0065-2458(06)69001-3_bib065","doi-asserted-by":"crossref","DOI":"10.1147\/rd.446.0851","article-title":"A performance methodology for commercial servers","author":"Kunkel","year":"2000","journal-title":"IBM Journal of R&D"},{"key":"10.1016\/S0065-2458(06)69001-3_bib066","doi-asserted-by":"crossref","unstructured":"Laudon J., \u201cPerformance\/watt the new server focus\u201d, in: The First Workshop on Design, Architecture, and Simulation of Chip-Multiprocessors, November 2005","DOI":"10.1145\/1105734.1105737"},{"key":"10.1016\/S0065-2458(06)69001-3_bib067","unstructured":"Li J., Martinez J., \u201cPower-performance implications of thread-level parallelism in chip multiprocessors\u201d, in: Proceedings of International Symposium on Performance Analysis of Systems and Software, 2005"},{"key":"10.1016\/S0065-2458(06)69001-3_bib068","unstructured":"Lovett T., Thakkar S., \u201cThe symmetry multiprocessor system\u201d, in: International Conference on Parallel Processing, August 1988"},{"key":"10.1016\/S0065-2458(06)69001-3_bib069","unstructured":"Merritt R., \u201cDesigners cut fresh paths to parallelism\u201d, in: EE Times, October 1999"},{"issue":"8","key":"10.1016\/S0065-2458(06)69001-3_bib070","article-title":"Cramming more components onto integrated circuits","volume":"38","author":"Moore","year":"1965","journal-title":"Electronics"},{"key":"10.1016\/S0065-2458(06)69001-3_bib071","unstructured":"Morad T., Weiser U., Kolodny A., \u201cACCMP\u2014asymmetric cluster chip-multiprocessing\u201d, CCIT Technical Report 488, 2004"},{"key":"10.1016\/S0065-2458(06)69001-3_bib072","article-title":"Performance, power efficiency and scalability of asymmetric cluster chip multiprocessors","volume":"4","author":"Morad","year":"2005","journal-title":"Computer Architecture Letters"},{"issue":"2","key":"10.1016\/S0065-2458(06)69001-3_bib073","doi-asserted-by":"crossref","DOI":"10.1109\/4.68123","article-title":"An area model for on-chip memories and its applications","volume":"26","author":"Mulder","year":"1991","journal-title":"IEEE Journal of Solid State Circuits"},{"key":"10.1016\/S0065-2458(06)69001-3_bib074","unstructured":"Papamarcos M., Patel J., \u201cA low overhead coherence solution for multiprocessors with private cache memories\u201d, in: International Symposium on Computer Architecture, 1988"},{"key":"10.1016\/S0065-2458(06)69001-3_bib075","unstructured":"Rabaey J.M., \u201cThe quest for ultra-low energy computation opportunities for architectures exploiting low-current devices\u201d, April 2000"},{"key":"10.1016\/S0065-2458(06)69001-3_bib076","doi-asserted-by":"crossref","unstructured":"Sankaralingam K., Nagarajan R., Liu H., Kim C., Huh J., Burger D., Keckler S.W., Moore C.R., \u201cExploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture\u201d, in: International Symposium on Computer Architecture, June 2003","DOI":"10.1145\/859666.859667"},{"key":"10.1016\/S0065-2458(06)69001-3_bib077","doi-asserted-by":"crossref","unstructured":"Sherwood T., Perelman E., Hamerly G., Calder B., \u201cAutomatically characterizing large scale program behavior\u201d, in: Tenth International Conference on Architectural Support for Programming Languages and Operating Systems, October 2002","DOI":"10.1145\/605397.605403"},{"key":"10.1016\/S0065-2458(06)69001-3_bib078","doi-asserted-by":"crossref","unstructured":"Sherwood T., Perelman E., Hamerly G., Sair S., Calder B., \u201cDiscovering and exploiting program phases\u201d, in: IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, December 2003","DOI":"10.1109\/MM.2003.1261391"},{"key":"10.1016\/S0065-2458(06)69001-3_bib079","doi-asserted-by":"crossref","unstructured":"Sherwood T., Perelman E., Hamerly G., Calder B., \u201cAutomatically characterizing large-scale program behavior\u201d, in: International Conference on Architectural Support for Programming Languages and Operating Systems, October 2002","DOI":"10.1145\/605397.605403"},{"key":"10.1016\/S0065-2458(06)69001-3_bib080","unstructured":"Shivakumar P., Jouppi N., \u201cCACTI 3.0: An integrated cache timing, power and area model\u201d, Technical Report 2001\/2, Compaq Computer Corporation, August 2001"},{"key":"10.1016\/S0065-2458(06)69001-3_bib081","doi-asserted-by":"crossref","unstructured":"Snavely A., Tullsen D., \u201cSymbiotic jobscheduling for a simultaneous multithreading architecture\u201d, in: Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, November 2000","DOI":"10.1145\/378993.379244"},{"key":"10.1016\/S0065-2458(06)69001-3_bib082","unstructured":"SPEC, Spec cpu2000 documentation, http:\/\/www.spec.org\/osg\/cpu2000\/docs\/"},{"key":"10.1016\/S0065-2458(06)69001-3_bib083","unstructured":"Sun, UltrasparcIV, http:\/\/siliconvalley.internet.com\/news\/print.php\/3090801"},{"key":"10.1016\/S0065-2458(06)69001-3_bib084","series-title":"The 36th Annual IEEE\/ACM International Symposium on Microarchitecture","first-page":"291","article-title":"Wavescalar","author":"Swanson","year":"2003"},{"key":"10.1016\/S0065-2458(06)69001-3_bib085","doi-asserted-by":"crossref","DOI":"10.1147\/rd.443.0379","article-title":"The future of interconnection technology","author":"Theis","year":"2000","journal-title":"IBM Journal of R&D"},{"key":"10.1016\/S0065-2458(06)69001-3_bib086","unstructured":"Tremblay M., \u201cMajc-5200: A VLIW convergent mpsoc\u201d, in: Microprocessor Forum, October 1999"},{"key":"10.1016\/S0065-2458(06)69001-3_bib087","unstructured":"Tullsen D., \u201cSimulation and modeling of a simultaneous multithreading processor\u201d, in: 22nd Annual Computer Measurement Group Conference, December 1996"},{"key":"10.1016\/S0065-2458(06)69001-3_bib088","unstructured":"Tullsen D., Brown J., \u201cHandling long-latency loads in a simultaneous multithreading processor\u201d, in: 34th International Symposium on Microarchitecture, December 2001"},{"key":"10.1016\/S0065-2458(06)69001-3_bib089","doi-asserted-by":"crossref","unstructured":"Tullsen D., Eggers S., Emer J., Levy H., Lo J., Stamm R., \u201cExploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor\u201d, in: 23rd Annual International Symposium on Computer Architecture, May 1996","DOI":"10.1145\/232973.232993"},{"key":"10.1016\/S0065-2458(06)69001-3_bib090","doi-asserted-by":"crossref","unstructured":"Tullsen D., Eggers S., Levy H., \u201cSimultaneous multithreading: Maximizing on-chip parallelism\u201d, in: 22nd Annual International Symposium on Computer Architecture, June 1995","DOI":"10.1109\/ISCA.1995.524578"},{"issue":"9","key":"10.1016\/S0065-2458(06)69001-3_bib091","doi-asserted-by":"crossref","first-page":"86","DOI":"10.1109\/2.612254","article-title":"Baring it all to software: Raw machines","volume":"30","author":"Waingold","year":"1997","journal-title":"Computer"},{"key":"10.1016\/S0065-2458(06)69001-3_bib092","doi-asserted-by":"crossref","unstructured":"Wall D., \u201cLimits of instruction-level parallelism\u201d, in: International Symposium on Architectural Support for Programming Languages and Operating Systems, April 1991, pp. 176\u2013188","DOI":"10.1145\/106972.106991"},{"key":"10.1016\/S0065-2458(06)69001-3_bib093","doi-asserted-by":"crossref","DOI":"10.1147\/rd.461.0027","article-title":"The circuit and physical design of the Power4 microprocessor","author":"Warnock","year":"2002","journal-title":"IBM Journal of R&D"},{"key":"10.1016\/S0065-2458(06)69001-3_bib094","doi-asserted-by":"crossref","unstructured":"Wilson A., \u201cHierarchical cache\/bus architecture for shared memory multiprocessors\u201d, in: International Symposium on Computer Architecture, June 1987","DOI":"10.1145\/30350.30378"},{"key":"10.1016\/S0065-2458(06)69001-3_bib095","doi-asserted-by":"crossref","unstructured":"Zyuban V., \u201cUnified architecture level energy-efficiency metric\u201d, in: 2002 Great Lakes Symposium on VLSI, April 2002","DOI":"10.1145\/505306.505313"}],"container-title":["Advances in Computers","Architectural Issues"],"original-title":[],"language":"en","deposited":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T22:34:54Z","timestamp":1740868494000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0065245806690013"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007]]},"ISBN":["9780123737458"],"references-count":95,"URL":"https:\/\/doi.org\/10.1016\/s0065-2458(06)69001-3","relation":{},"ISSN":["0065-2458"],"issn-type":[{"type":"print","value":"0065-2458"}],"subject":[],"published":{"date-parts":[[2007]]}}}