{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,24]],"date-time":"2025-08-24T23:00:29Z","timestamp":1756076429832},"reference-count":138,"publisher":"Elsevier","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[1981]]},"DOI":"10.1016\/s0065-2458(08)60497-0","type":"book-chapter","created":{"date-parts":[[2011,1,19]],"date-time":"2011-01-19T05:56:15Z","timestamp":1295416575000},"page":"115-197","source":"Crossref","is-referenced-by-count":15,"title":["Vector Computer Architecture and Processing Techniques"],"prefix":"10.1016","author":[{"given":"Kai","family":"Hwang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shun-Piao","family":"Su","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lionel M.","family":"Ni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S0065-2458(08)60497-0_bib1","series-title":"\u201cAmdahl 470 V\/6 Machine Reference Manual.\u201d","author":"Amdahl Corp.","year":"1975"},{"issue":"No. 1","key":"10.1016\/S0065-2458(08)60497-0_bib2","doi-asserted-by":"crossref","first-page":"34","DOI":"10.1147\/rd.111.0034","article-title":"The IBM system\/360 model 91: Floating-point execution unit","volume":"11","author":"Anderson","year":"1967","journal-title":"IBM J. Res. Dev."},{"key":"10.1016\/S0065-2458(08)60497-0_bib3","series-title":"\u201cComputer Systems Architectures.\u201d","author":"Baer","year":"1980"},{"key":"10.1016\/S0065-2458(08)60497-0_bib4","unstructured":"Banerjee, U., Gajski, D., and Kuck, D. (1980). Array machine control units for loops containing IFs. Proc. Int. Conf. Parallel Process. 1980 pp. 28\u201336."},{"issue":"No. 8","key":"10.1016\/S0065-2458(08)60497-0_bib5","doi-asserted-by":"crossref","first-page":"746","DOI":"10.1109\/TC.1968.229158","article-title":"The ILLIAC IV computer","volume":"C-17","author":"Barnes","year":"1968","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib6","series-title":"\u201cHigh Speed Computer and Algorithm Organization\u201d","first-page":"71","article-title":"An evaluation of the CRAY-1 computer","author":"Baskett","year":"1977"},{"key":"10.1016\/S0065-2458(08)60497-0_bib7","unstructured":"Batcher, K. E. (1974). STARAN parallel processor system hardware. Proc. Natl. Comput. Conf. (AFIPS Press), 43, 405\u2013410."},{"key":"10.1016\/S0065-2458(08)60497-0_bib8","unstructured":"Batcher, K. E. (1976). The flip network in STARAN. Proc. Int. Conf. Parallel Process. 1976 pp. 65\u201371."},{"issue":"No. 2","key":"10.1016\/S0065-2458(08)60497-0_bib9","doi-asserted-by":"crossref","first-page":"174","DOI":"10.1109\/TC.1977.5009297","article-title":"The multi-dimensional access memory in STARAN","volume":"C-26","author":"Batcher","year":"1977","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib10","doi-asserted-by":"crossref","first-page":"836","DOI":"10.1109\/TC.1980.1675684","article-title":"Design of a massively parallel processor","volume":"C-29","author":"Batcher","year":"1980","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib11","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/MSPEC.1981.6369534","article-title":"Minis and mainframes: Design changes are spurred by LSI","author":"Bernhard","year":"1981","journal-title":"IEEE Spectrum"},{"issue":"No. 4","key":"10.1016\/S0065-2458(08)60497-0_bib12","doi-asserted-by":"crossref","first-page":"369","DOI":"10.1109\/PROC.1972.8647","article-title":"The Illiac IV system","volume":"60","author":"Bouknight","year":"1972","journal-title":"Proc. IEEE"},{"key":"10.1016\/S0065-2458(08)60497-0_bib13","series-title":"\u201cComputer Architectures and Networks\u201d","first-page":"99","article-title":"Models and evaluation of pipeline systems","author":"Bovet","year":"1976"},{"key":"10.1016\/S0065-2458(08)60497-0_bib14","doi-asserted-by":"crossref","unstructured":"Briggs, F. A. (1978). Performance of memory configurations for parallel-pipelined computers. Proc. 5th Annu. Symp. Comput. Archit. pp. 202\u2013209.","DOI":"10.1145\/800094.803049"},{"issue":"No. 2","key":"10.1016\/S0065-2458(08)60497-0_bib15","doi-asserted-by":"crossref","first-page":"162","DOI":"10.1109\/TC.1977.5009295","article-title":"Organization of semiconductor memories for parallel-pipelined processors","volume":"C-26","author":"Briggs","year":"1977","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib16","doi-asserted-by":"crossref","unstructured":"Briggs, F. A., Fu, K. S., Hwang, K., and Patel, J. H. (1979). \u201cPM4: A reconfigurable multiprocessor system for pattern recognition and image processing. Proc. NCC, AFIPS 1979 pp. 255\u2013265.","DOI":"10.1109\/MARK.1979.8817082"},{"key":"10.1016\/S0065-2458(08)60497-0_bib17","unstructured":"Burroughs Co. (1977). \u201cBSP: Implementation of FORTRAN,\u201d Doc. 61391, Nov."},{"key":"10.1016\/S0065-2458(08)60497-0_bib18","unstructured":"Burroughs Co. (1978). \u201cBSP: Overview Perspective, and Architecture,\u201d Doc. 61391, Feb."},{"issue":"No. 8","key":"10.1016\/S0065-2458(08)60497-0_bib19","doi-asserted-by":"crossref","first-page":"689","DOI":"10.1109\/TC.1980.1675650","article-title":"Multiple-read single-write memory and its applications","volume":"C-29","author":"Chang","year":"1980","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib20","first-page":"69","article-title":"Parallelism, pipelining, and computer efficiency","author":"Chen","year":"1971","journal-title":"Comput. Des."},{"key":"10.1016\/S0065-2458(08)60497-0_bib21","series-title":"\u201cIntroduction to Computer Architecture\u201d","first-page":"427","article-title":"Overlap and pipeline processing","author":"Chen","year":"1980"},{"key":"10.1016\/S0065-2458(08)60497-0_bib22","unstructured":"Cheung, L., and Mowle, F. J. (1974). Suggestions for improvements to a pipelined computer system. Proc. 12th Annu. Allerton Conf. Circuit Syst. Theory pp. 670\u2013677."},{"key":"10.1016\/S0065-2458(08)60497-0_bib23","series-title":"\u201cControl Data STAR-100 Features Manual,\u201d","author":"Control Data Corp.","year":"1973"},{"key":"10.1016\/S0065-2458(08)60497-0_bib24","unstructured":"Control Data Corp. (1976). \u201cControl Data STAR-100 FORTRAN Language Version 2 Reference Manual,\u201d Publ. No. 60386200. CDC, St. Paul, Minnesota."},{"key":"10.1016\/S0065-2458(08)60497-0_bib25","series-title":"\u201cIntroducing the Control Data CYBER-205: The Supercomputer for the 80\u2032s.\u201d","author":"Control Data Corp.","year":"1980"},{"issue":"No. 11","key":"10.1016\/S0065-2458(08)60497-0_bib26","doi-asserted-by":"crossref","first-page":"1123","DOI":"10.1109\/TC.1977.1674758","article-title":"The distributed pipeline","volume":"C-26","author":"Cooper","year":"1977","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib27","unstructured":"Cordennier, V. (1975). A two dimension pipelined processor for communication in a parallel system. Proc. Sagamore Comp. Conf. Parallel Process. 1975 pp. 115\u2013121."},{"key":"10.1016\/S0065-2458(08)60497-0_bib28","unstructured":"Cray Research, Inc. (1977). \u201cCRAY-1 Computer System Hardware Reference Manual,\u201d Publ. No. 2240004. Bloomington, Minnesota."},{"key":"10.1016\/S0065-2458(08)60497-0_bib29","unstructured":"Cray Research, Inc. (1978). \u201cCRAY-1 Computer System Preliminary CRAY FORTRAN (CFT) Reference Manual,\u201d Publ. No. 2240009. Bloomington, Minnesota."},{"key":"10.1016\/S0065-2458(08)60497-0_bib30","unstructured":"Datawest Corp. (1979). \u201cReal Time Series of Microprogrammable Array Transform Processors,\u201d Prod. Bull. Ser. B."},{"key":"10.1016\/S0065-2458(08)60497-0_bib31","unstructured":"Davidson, E. S. (1971). The design and control of pipelined function generators. Proc. Int. IEEE Conf. Syst., Networks, Comput., Oaxtepec, Mexico, Jan., 1971."},{"key":"10.1016\/S0065-2458(08)60497-0_bib32","first-page":"181","article-title":"Effective control for pipelined computers","author":"Davidson","year":"1975","journal-title":"COMPCON Proc. IEEE Computer Soc."},{"issue":"No. 10","key":"10.1016\/S0065-2458(08)60497-0_bib33","first-page":"113","article-title":"The CRAY-1 at Los Alamos","volume":"24","author":"Dorr","year":"1978","journal-title":"Datamation"},{"key":"10.1016\/S0065-2458(08)60497-0_bib34","unstructured":"Emer, J. S., and Davidson, E. S. (1978). Control store organization for multiple stream pipelined processors. Proc. Int. Conf. Parallel Process. 1978 pp. 43\u201348."},{"key":"10.1016\/S0065-2458(08)60497-0_bib35","unstructured":"Evansen, A. J., and Troy, J. L. (1973). Introduction to the architecture of a 288\u2013element PEPE. Proc. Sagamore Conf. Parallel Process. 1973 pp. 162\u2013169."},{"issue":"No. 3","key":"10.1016\/S0065-2458(08)60497-0_bib36","doi-asserted-by":"crossref","first-page":"309","DOI":"10.1109\/T-C.1974.223927","article-title":"Data manipulation functions in parallel processors and their implementations","volume":"C-23","author":"Feng","year":"1974","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib37","unstructured":"Floating Point System, Inc. (1976). \u201cAP-120B Processor Handbook,\u201d Publ. No. 7259\u201302, May. Portland, Oregon."},{"issue":"No. 9","key":"10.1016\/S0065-2458(08)60497-0_bib38","doi-asserted-by":"crossref","first-page":"948","DOI":"10.1109\/TC.1972.5009071","article-title":"Some computer organization and their effectiveness","volume":"C-21","author":"Flynn","year":"1972","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib39","first-page":"1","article-title":"Cellular vector computer of vertical and horizontal processing with vertical common memory","author":"Gao","year":"1979","journal-title":"J. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib40","unstructured":"Gao, Q. S., and Zhang, X. (1980). Another approach to making supercomputer by microprocessors\u2013cellular vector computer of vertical and horizontal processing with virtual common memory. Proc. Int. Conf. Parallel Process. 1980 pp. 163\u2013164."},{"key":"10.1016\/S0065-2458(08)60497-0_bib41","series-title":"\u201cHigh Speed Computer and Algorithm Organization\u201d","first-page":"461","article-title":"Some numerical effects of a FORTRAN vectorizing compiler on a Texas instruments advanced scientific computer","author":"Ginsberg","year":"1977"},{"key":"10.1016\/S0065-2458(08)60497-0_bib42","unstructured":"Goodyear Aerospace Co. (1979). \u201cMassively Parallel Processor (MPP),\u201d Tech. Rep. GER-16684, July, Akron, Ohio."},{"issue":"No. 4","key":"10.1016\/S0065-2458(08)60497-0_bib43","first-page":"68","article-title":"The parallel and the pipeline computers","volume":"16","author":"Graham","year":"1970","journal-title":"Datamation"},{"issue":"No. 9","key":"10.1016\/S0065-2458(08)60497-0_bib44","doi-asserted-by":"crossref","first-page":"880","DOI":"10.1109\/TC.1972.5009044","article-title":"Pipelining of arithmetic functions","volume":"C-21","author":"Hallin","year":"1972","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib45","unstructured":"H\u00e4ndler, W. (1977). The impact of classification schemes on computer architecture. Proc. Int. Conf. Parallel Process. 1977 pp. 7\u201315."},{"key":"10.1016\/S0065-2458(08)60497-0_bib46","series-title":"\u201cComputer Architecture and Organization.\u201d","author":"Hayes","year":"1978"},{"key":"10.1016\/S0065-2458(08)60497-0_bib47","unstructured":"Higbie, L. C. (1972). The OMEN computer: Associative array processor. Digest of Papers IEEE COMPCON pp. 287\u2013290."},{"issue":"No. 4","key":"10.1016\/S0065-2458(08)60497-0_bib48","first-page":"139","article-title":"Applications of vector processing.\u201d","volume":"17","author":"Higbie","year":"1978","journal-title":"Comput. Des."},{"key":"10.1016\/S0065-2458(08)60497-0_bib49","unstructured":"Hintz, R. G., and Tate, D. P. (1972). Control data STAR-100 processor design. Digest of Papers, IEEE COMPCON Proc. Sept., pp. 1\u20134."},{"issue":"No. 3","key":"10.1016\/S0065-2458(08)60497-0_bib50","first-page":"151","article-title":"Comparison of selected array processor architecture","volume":"18","author":"Hufnagel","year":"1979","journal-title":"Comput. Des."},{"key":"10.1016\/S0065-2458(08)60497-0_bib51","series-title":"\u201cComputer Arithmetic: Principles, Architecture and Design.\u201d","author":"Hwang","year":"1979"},{"key":"10.1016\/S0065-2458(08)60497-0_bib52","doi-asserted-by":"crossref","first-page":"300","DOI":"10.1109\/TC.1979.1675350","article-title":"Global and modular two's complement array multiplies","volume":"C-28","author":"Hwang","year":"1979","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib53","unstructured":"Hwang, K., and Cheng, Y. H. (1980). VLSI arithmetic arrays and modular networks for solving large-scale linear system of equations. Proc. Int. Conf. Parallel Process. 1980 pp. 217\u2013227."},{"key":"10.1016\/S0065-2458(08)60497-0_bib54","unstructured":"Hwang, K., and Ni, L. M. (1979). Performance evaluation and resource optimization of multiple SIMD computer organizations. Proc. Int. Conf. Parallel Process. 1979 pp. 86\u201394."},{"key":"10.1016\/S0065-2458(08)60497-0_bib55","doi-asserted-by":"crossref","first-page":"831","DOI":"10.1109\/TC.1980.1675683","article-title":"Resource optimization of a parallel computer for multiple vector processing","volume":"C-29","author":"Hwang","year":"1980","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib56","series-title":"\u201cVector Processing Computer Architectures,\u201d","author":"Hwang","year":"1980"},{"key":"10.1016\/S0065-2458(08)60497-0_bib57","unstructured":"Hwang, K., and Cheng, Y. H. (1981). \u201cPartitioned Algorithms and VLSI Structures for Large-Scale Matrix Computations in Solving Linear Equations,\u201dProc. 5th Symp. Comput. Arithmetic, IEEE Comput. Soc., May 18\u201319, Ann Arbor, 1981."},{"issue":"No. 1","key":"10.1016\/S0065-2458(08)60497-0_bib58","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1093\/comjnl\/15.1.42","article-title":"The MU5 instruction pipeline","volume":"15","author":"Ibbett","year":"1972","journal-title":"Comput. J."},{"key":"10.1016\/S0065-2458(08)60497-0_bib59","unstructured":"IBM, Inc. (1977). \u201cIBM 3838 Array Processor Functional Characteristics,\u201d Form No. GA 24\u20133639. Armond, New York."},{"key":"10.1016\/S0065-2458(08)60497-0_bib60","doi-asserted-by":"crossref","unstructured":"Irwin, M. J. (1978). A pipelined processing unit for on-line division. Proc. Symp. Comput. Archit., 5th 1978 pp. 24\u201330.","DOI":"10.1145\/800094.803023"},{"key":"10.1016\/S0065-2458(08)60497-0_bib61","unstructured":"Jin, L. (1980). A new general-purpose distributed multiprocessor structure. Proc. Int. Conf. Parallel Process. 1980 pp. 153\u2013154."},{"key":"10.1016\/S0065-2458(08)60497-0_bib62","series-title":"\u201cCRAY-1 Computer System.\u201d","author":"Johnson","year":"1977"},{"issue":"No. 2","key":"10.1016\/S0065-2458(08)60497-0_bib63","first-page":"89","article-title":"An introduction to vector processing","volume":"17","author":"Johnson","year":"1978","journal-title":"Comput. Des."},{"issue":"No. 9","key":"10.1016\/S0065-2458(08)60497-0_bib64","doi-asserted-by":"crossref","first-page":"855","DOI":"10.1109\/TC.1978.1675205","article-title":"Effective pipelining of digital systems","volume":"C-27","author":"Jump","year":"1978","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib65","doi-asserted-by":"crossref","first-page":"1114","DOI":"10.1109\/TC.1980.1675517","article-title":"Problems of designing supersystems with dynamic architectures","author":"Kartashev","year":"1980","journal-title":"IEEE Trans. Computer"},{"key":"10.1016\/S0065-2458(08)60497-0_bib66","first-page":"270","article-title":"Vector processing, problem or opportunity?","author":"Kascic","year":"1980","journal-title":"COMPCON Proc."},{"issue":"No. 11","key":"10.1016\/S0065-2458(08)60497-0_bib67","doi-asserted-by":"crossref","first-page":"1169","DOI":"10.1109\/T-C.1974.223825","article-title":"An almost-optimal algorithm for the assembly line scheduling problem","volume":"C-23","author":"Kaufman","year":"1974","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib68","unstructured":"K. Kennedy Optimization of vector operations in an extended fortran compiler IBM Res. Rep. RC-7784 1979"},{"issue":"No. 11","key":"10.1016\/S0065-2458(08)60497-0_bib69","doi-asserted-by":"crossref","first-page":"71","DOI":"10.1109\/MC.1980.1653422","article-title":"Second generation of vector supercomputers","volume":"13","author":"Kozdrowicki","year":"1980","journal-title":"IEEE Comput. Mag."},{"issue":"No. 8","key":"10.1016\/S0065-2458(08)60497-0_bib70","doi-asserted-by":"crossref","first-page":"758","DOI":"10.1109\/TC.1968.229159","article-title":"ILLIAC IV software and application programming","volume":"C-17","author":"Kuck","year":"1968","journal-title":"IEEE Trans. Comput."},{"issue":"No. 1","key":"10.1016\/S0065-2458(08)60497-0_bib71","doi-asserted-by":"crossref","first-page":"29","DOI":"10.1145\/356683.356686","article-title":"A survey of parallel machine organization and programming","volume":"9","author":"Kuck","year":"1977","journal-title":"Comput. Surv."},{"key":"10.1016\/S0065-2458(08)60497-0_bib72","volume":"1","author":"Kuck","year":"1978"},{"key":"10.1016\/S0065-2458(08)60497-0_bib73","series-title":"\u201cSpare Matrix Proceedings\u201d","first-page":"245","article-title":"Systolic arrays (for VLSI)","author":"Kung","year":"1978"},{"key":"10.1016\/S0065-2458(08)60497-0_bib74","doi-asserted-by":"crossref","unstructured":"Lang, D. E., Agerwala, T. K., and Chandy, K. M. (1979). A modeling approach and design tool for pipelined central processors. Proc. 6th Annu. Symp. Comput. Archit. IEEE Computer Soc., pp. 122\u2013129.","DOI":"10.1145\/800090.802901"},{"key":"10.1016\/S0065-2458(08)60497-0_bib75","series-title":"\u201cCost-effective processor design with an application to fast Fourier transform computers.\u201d","author":"Larson","year":"1973"},{"key":"10.1016\/S0065-2458(08)60497-0_bib76","unstructured":"Larson, A. G., and Davidson, E. S. (1973). Cost-effective design of special-purpose processors: A fast Fourier transform case study. Proc. Allerton Conf., 11th 1973 pp. 547\u2013557."},{"issue":"No. 12","key":"10.1016\/S0065-2458(08)60497-0_bib77","doi-asserted-by":"crossref","first-page":"1145","DOI":"10.1109\/T-C.1975.224157","article-title":"Access and alignment of data in an array processor","volume":"C-24","author":"Lawrie","year":"1975","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib78","unstructured":"Lawrie, D. H., and Vora, C. (1980). The prime memory system for array access. Proc. Int. Conf. Parallet Processing 1980 pp. 81\u201387."},{"key":"10.1016\/S0065-2458(08)60497-0_bib79","unstructured":"Lee, R. B.-L. (1980). Empirical results on the speed, efficiency, redundancy and quality of parallel computations. Proc. Int. Conf. Parallel Process. 1980, pp. 91\u201396."},{"issue":"1","key":"10.1016\/S0065-2458(08)60497-0_bib80","doi-asserted-by":"crossref","first-page":"121","DOI":"10.1145\/321992.322000","article-title":"Program improvement by source-to-source transformation","volume":"24","author":"Loveman","year":"1977","journal-title":"J. Assoc. Comput. Mach."},{"issue":"No. 11","key":"10.1016\/S0065-2458(08)60497-0_bib81","doi-asserted-by":"crossref","first-page":"1132","DOI":"10.1109\/TC.1976.1674565","article-title":"Some comments concerning design of pipeline arithmetic arrays","volume":"C-25","author":"Majithia","year":"1976","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib82","unstructured":"Mayeda, W. (1975). Two Methods for improving throughput of a pipeline. Proc. Allerton Conf., 13th 1975 pp. 873\u2013886."},{"key":"10.1016\/S0065-2458(08)60497-0_bib83","unstructured":"Naga, N. M., and Field, J. A. (1978). A pipelined direct execution high level language machine. Proc. Int. Conf. Parallel Process. 1978 pp. 49\u201351."},{"key":"10.1016\/S0065-2458(08)60497-0_bib84","unstructured":"Nassimi, D., and Sahni, S. H. (1980). Data broadcasting in SIMD computers. Proc. Int. Conf. Parallel Process. 1980 pp. 325\u2013326."},{"key":"10.1016\/S0065-2458(08)60497-0_bib85","first-page":"265","article-title":"Multi-precise arithmetic on a vector processor, or how we found the 27th Mersenne prime","author":"Nelson","year":"1980","journal-title":"COMPCON Proc."},{"issue":"No. 4","key":"10.1016\/S0065-2458(08)60497-0_bib86","doi-asserted-by":"crossref","DOI":"10.1109\/TSE.1981.234541","article-title":"Performance modeling of shared resource array processor","volume":"SE-7","author":"Ni","year":"1981","journal-title":"IEEE Trans. Software Eng."},{"issue":"No. 6","key":"10.1016\/S0065-2458(08)60497-0_bib87","doi-asserted-by":"crossref","first-page":"514","DOI":"10.1109\/TC.1977.1674877","article-title":"Memory and bus conflict in an array processor","volume":"C-26","author":"Nutt","year":"1977","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib88","doi-asserted-by":"crossref","unstructured":"Owens, R. M., and Irwin, M. J. (1979). On-line algorithms for the design of pipeline architecture. Proc. 6th Annu. Symp. Comput. Archit, pp. 12\u201319.","DOI":"10.1145\/800090.802888"},{"key":"10.1016\/S0065-2458(08)60497-0_bib89","doi-asserted-by":"crossref","first-page":"763","DOI":"10.1109\/TC.1980.1675676","article-title":"High-speed multiprocessors and compilation techniques","volume":"C-29","author":"Padua","year":"1980","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib90","first-page":"225","article-title":"Pipelined architectures for microprocessor","author":"Parasuraman","year":"1976","journal-title":"COMPCON Proc."},{"key":"10.1016\/S0065-2458(08)60497-0_bib91","doi-asserted-by":"crossref","unstructured":"Patel, J. H. (1976a). Improving the throughput of a pipeline by insertion of delays. Proc. 3rd Annu. Symp. Comput. Archit. pp. 159\u2013164. IEEE Computer Soc.","DOI":"10.1145\/633617.803575"},{"key":"10.1016\/S0065-2458(08)60497-0_bib92","series-title":"Improving the throughput of pipelines with delays and buffers","author":"Patel","year":"1976"},{"key":"10.1016\/S0065-2458(08)60497-0_bib93","doi-asserted-by":"crossref","unstructured":"Patel, J. H. (1978a). Pipelines with internal buffers. Proc. 5th Annu. Symp. Comput. Archit. pp. 249\u2013254. IEEE Computer Soc.","DOI":"10.1145\/800094.803057"},{"key":"10.1016\/S0065-2458(08)60497-0_bib94","unstructured":"Patel, J. H. (1978b). Performance studies of internally buffered pipelines. Proc. Int. Conf. Parallel Process. 1978 pp. 36\u201342."},{"key":"10.1016\/S0065-2458(08)60497-0_bib95","doi-asserted-by":"crossref","unstructured":"Patel, J. H. (1979). Processor-memory interconnections for multiprocessors. Proc. 6th Annu. Symp. Comput. Archit. pp. 168\u2013177. IEEE Computer Soc.","DOI":"10.1145\/800090.802906"},{"key":"10.1016\/S0065-2458(08)60497-0_bib96","unstructured":"G. Paul Large-scale vector\/array processors IBM Res. Rep. RC 7306 1978 1 24"},{"key":"10.1016\/S0065-2458(08)60497-0_bib97","unstructured":"G. Paul M.W. Wilson An introduction to VECTRAN and its use in scientific applications programming IBM Res. Rep. RC 7287 1978"},{"key":"10.1016\/S0065-2458(08)60497-0_bib98","doi-asserted-by":"crossref","first-page":"458","DOI":"10.1109\/TC.1977.1674863","article-title":"The indirect binary n-cube microprocessor array","volume":"C-25","author":"Pease","year":"1977","journal-title":"IEEE Trans. Comput."},{"issue":"No. 9","key":"10.1016\/S0065-2458(08)60497-0_bib99","doi-asserted-by":"crossref","first-page":"777","DOI":"10.1109\/TC.1980.1675677","article-title":"A uniform representation of single-and multistage interconnection networks used in SIMD machines","volume":"C-29","author":"Pradhan","year":"1980","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib100","unstructured":"Purcell, C. J. (1974). The control data STAR-100\u2013performance measurements. Proc. Natl. Comput. Conf. 43, pp. 385\u2013387. AFIPS Press."},{"key":"10.1016\/S0065-2458(08)60497-0_bib101","doi-asserted-by":"crossref","unstructured":"Radoy, C. H., and Lipovski, G. J. (1974). Switched multiple instruction, multiple data stream processing. Proc. 2nd Annu. Symp. Comput. Archit, pp. 183\u2013187.","DOI":"10.1145\/641675.642120"},{"key":"10.1016\/S0065-2458(08)60497-0_bib102","doi-asserted-by":"crossref","first-page":"289","DOI":"10.1145\/1500175.1500235","article-title":"Pipelining\u2013the generalized concept and sequencing strategies","author":"Ramamoorthy","year":"1974","journal-title":"AFIPS NCC Proc."},{"key":"10.1016\/S0065-2458(08)60497-0_bib103","doi-asserted-by":"crossref","first-page":"625","DOI":"10.1145\/1500175.1500297","article-title":"Efficiency in generalized pipeline networks","author":"Ramamoorthy","year":"1974","journal-title":"AFIPS NCC Proc."},{"key":"10.1016\/S0065-2458(08)60497-0_bib104","unstructured":"Ramamoorthy, C. V., and Li, H. F. (1975). Sequencing control in multifunctional pipeline systems. Proc. Sagamore Comp. Conf. Parallel Processing 1975 pp. 79\u201389."},{"issue":"No. 1","key":"10.1016\/S0065-2458(08)60497-0_bib105","doi-asserted-by":"crossref","first-page":"61","DOI":"10.1145\/356683.356687","article-title":"Pipeline architecture","volume":"9","author":"Ramamoorthy","year":"1977","journal-title":"Comput. Surv."},{"key":"10.1016\/S0065-2458(08)60497-0_bib106","series-title":"\u201cHigh Speed Computer and Algorithm Organization\u201d","first-page":"399","article-title":"To vectorize or to \u201cvectorize\u201d: That is the question","author":"Remund","year":"1977"},{"issue":"No. 2","key":"10.1016\/S0065-2458(08)60497-0_bib107","doi-asserted-by":"crossref","first-page":"144","DOI":"10.1109\/TC.1978.1675047","article-title":"Two-dimensional microprocessor pipelines for image processing","volume":"C-27","author":"Roesser","year":"1978","journal-title":"IEEE Trans. Comput."},{"issue":"No. 1","key":"10.1016\/S0065-2458(08)60497-0_bib108","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1145\/359327.359336","article-title":"The CRAY-1 computer system","volume":"21","author":"Russell","year":"1978","journal-title":"Commun. ACM"},{"key":"10.1016\/S0065-2458(08)60497-0_bib109","series-title":"\u201cHigh Speed and Algorithm Organization\u201d","first-page":"129","article-title":"A complexity result on a pipelined processor design problem","author":"Schlankser","year":"1977"},{"key":"10.1016\/S0065-2458(08)60497-0_bib110","doi-asserted-by":"crossref","first-page":"161","DOI":"10.1016\/0096-0551(75)90015-6","article-title":"Optimization of very high level language. I. Value transmission and its corollaries","volume":"1","author":"Schwartz","year":"1978","journal-title":"J. Comput. Lang."},{"key":"10.1016\/S0065-2458(08)60497-0_bib111","first-page":"117","article-title":"Computer organization for array processing","author":"Senzig","year":"1965","journal-title":"AFIPS FJCC Proc."},{"issue":"No. 2","key":"10.1016\/S0065-2458(08)60497-0_bib112","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/MC.1974.6323457","article-title":"A multiminiprocessor system implemented through pipelining","volume":"7","author":"Shar","year":"1974","journal-title":"Computer"},{"issue":"No. 12","key":"10.1016\/S0065-2458(08)60497-0_bib113","doi-asserted-by":"crossref","first-page":"907","DOI":"10.1109\/TC.1979.1675280","article-title":"A model of SIMD machines and a comparison of various interconnection networks","volume":"C-28","author":"Siegel","year":"1979","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0065-2458(08)60497-0_bib114","unstructured":"Sintz, R. H. P. H. (1980). Optimal use of a vector processor. Digest of Papers, IEEE COMPCON, Spring 1980, pp. 277\u2013281."},{"key":"10.1016\/S0065-2458(08)60497-0_bib115","doi-asserted-by":"crossref","unstructured":"Sites, R. L. (1978). An analysis of the CRAY-1 computer. Proc. 5th Annu. Symp. Comput. Archit. pp. 101\u2013106.","DOI":"10.1145\/800094.803035"},{"key":"10.1016\/S0065-2458(08)60497-0_bib116","unstructured":"Smith, B. J. (1978). A pipelined, shared resources MIMD computer. Proc. Int. Conf. Parallel Process. 1978 pp. 6\u20138."},{"issue":"No. 4","key":"10.1016\/S0065-2458(08)60497-0_bib117","first-page":"2","article-title":"Array processing","volume":"2","author":"Sperry Rand","year":"1971","journal-title":"Sperry Rand Eng."},{"key":"10.1016\/S0065-2458(08)60497-0_bib118","unstructured":"Stephenson, C. M. (1973). Control of a variable configuration pipelined arithmetic unit. Proc. Allerton Conf., 11th 1973 pp. 558\u2013567."},{"key":"10.1016\/S0065-2458(08)60497-0_bib119","volume":"49","author":"Stevenson","year":"1980"},{"key":"10.1016\/S0065-2458(08)60497-0_bib120","series-title":"\u201cHigh Speed Computer and Algorithm Organization\u201d","first-page":"85","article-title":"Burroughs scientific processor","author":"Stokes","year":"1977"},{"issue":"No. 2","key":"10.1016\/S0065-2458(08)60497-0_bib121","doi-asserted-by":"crossref","first-page":"153","DOI":"10.1109\/T-C.1971.223205","article-title":"Parallel processing with the perfect shuffle","volume":"C-20","author":"Stone","year":"1971","journal-title":"IEEE Trans. Comput."},{"issue":"No. 2","key":"10.1016\/S0065-2458(08)60497-0_bib122","doi-asserted-by":"crossref","first-page":"138","DOI":"10.1109\/TSE.1978.231484","article-title":"Sorting on STAR","volume":"SE-4","author":"Stone","year":"1978","journal-title":"IEEE Trans. Software Eng."},{"key":"10.1016\/S0065-2458(08)60497-0_bib123","series-title":"\u201cIntroduction to Computer Architecture\u201d","first-page":"318","article-title":"Parallel computers","author":"Stone","year":"1980"},{"key":"10.1016\/S0065-2458(08)60497-0_bib124","unstructured":"Texas Instruments, Inc. (1971). \u201cDescription of the ASC System,\u201d Parts 1\u20135, Manual Nos. 934662\u2013934666."},{"key":"10.1016\/S0065-2458(08)60497-0_bib125","unstructured":"Texas Instruments, Inc. (1972). \u201cASC FORTRAN Reference Manual,\u201d Publ. No. 930044. Austin, Texas"},{"issue":"No. 4","key":"10.1016\/S0065-2458(08)60497-0_bib126","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1109\/MC.1974.6323500","article-title":"Special tutorial: Vector supercomputers","volume":"7","author":"Theis","year":"1974","journal-title":"IEEE Comput. Mag."},{"key":"10.1016\/S0065-2458(08)60497-0_bib127","unstructured":"Thomas, A. T., and Davidson, E. S. (1974). Scheduling of multiconfigurable pipelines. Proc. Allerton Conf., 12th 1972 pp. 658\u2013669."},{"key":"10.1016\/S0065-2458(08)60497-0_bib128","unstructured":"Thomasian, A., and Avizienis, A. (1975). A design study of a shared resource computing system. Proc. 3rd Annu. Symp. Comput. Archit. pp. 105\u2013112."},{"key":"10.1016\/S0065-2458(08)60497-0_bib129","series-title":"\u201cDesign of a Computer: The Control Data 6600.\u201d","author":"Thornton","year":"1970"},{"key":"10.1016\/S0065-2458(08)60497-0_bib130","series-title":"\u201cLarge Scale Computer Architecture\u2013Parallel and Associative Processors.\u201d","author":"Thurber","year":"1976"},{"issue":"No. 1","key":"10.1016\/S0065-2458(08)60497-0_bib131","first-page":"89","article-title":"Parallel processor architectures. Part I. General purpose system","volume":"18","author":"Thurber","year":"1979","journal-title":"Comput. Des."},{"issue":"No. 2","key":"10.1016\/S0065-2458(08)60497-0_bib132","first-page":"103","article-title":"Parallel processor architectures. Part II. Special purpose systems","volume":"18","author":"Thurber","year":"1979","journal-title":"Comput. Des."},{"issue":"No. 1","key":"10.1016\/S0065-2458(08)60497-0_bib133","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1147\/rd.111.0025","article-title":"An efficient algorithm for exploiting multiple arithmetic units","volume":"11","author":"Tomasulo","year":"1967","journal-title":"IBM J. Res. Dev."},{"key":"10.1016\/S0065-2458(08)60497-0_bib134","unstructured":"Vanaken, J., and Zick, G. (1978). The X-pipe: A pipeline for expression trees. Proc. Int. Conf. Parallel Process. 1978 pp. 238\u2013245."},{"key":"10.1016\/S0065-2458(08)60497-0_bib135","series-title":"The TI ASC\u2013a highly modular and flexible super computer architecture","author":"Watson","year":"1972"},{"key":"10.1016\/S0065-2458(08)60497-0_bib136","volume":"43","author":"Watson","year":"1974"},{"issue":"No. 3","key":"10.1016\/S0065-2458(08)60497-0_bib137","first-page":"93","article-title":"Array processor provides high throughput rates","volume":"17","author":"Wittmayer","year":"1978","journal-title":"Comput. Des."},{"issue":"No. 8","key":"10.1016\/S0065-2458(08)60497-0_bib138","doi-asserted-by":"crossref","first-page":"694","DOI":"10.1109\/TC.1980.1675651","article-title":"On a class of multistage interconnection networks","volume":"C-29","author":"Wu","year":"1980","journal-title":"IEEE Trans. Comput."}],"container-title":["Advances in Computers","Advances in Computers Volume 20"],"original-title":[],"deposited":{"date-parts":[[2020,6,15]],"date-time":"2020-06-15T19:42:21Z","timestamp":1592250141000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0065245808604970"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1981]]},"references-count":138,"URL":"https:\/\/doi.org\/10.1016\/s0065-2458(08)60497-0","relation":{},"ISSN":["0065-2458"],"issn-type":[{"value":"0065-2458","type":"print"}],"subject":[],"published":{"date-parts":[[1981]]}}}