{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,1,13]],"date-time":"2023-01-13T03:14:17Z","timestamp":1673579657922},"reference-count":12,"publisher":"Elsevier BV","issue":"4","license":[{"start":{"date-parts":[[2002,5,1]],"date-time":"2002-05-01T00:00:00Z","timestamp":1020211200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessors and Microsystems"],"published-print":{"date-parts":[[2002,5]]},"DOI":"10.1016\/s0141-9331(02)00013-3","type":"journal-article","created":{"date-parts":[[2002,10,14]],"date-time":"2002-10-14T18:58:33Z","timestamp":1034621913000},"page":"189-198","source":"Crossref","is-referenced-by-count":8,"title":["DRAM simulator for design and analysis of digital systems"],"prefix":"10.1016","volume":"26","author":[{"given":"Juha","family":"Alakarhu","sequence":"first","affiliation":[]},{"given":"Jarkko","family":"Niittylahti","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S0141-9331(02)00013-3_BIB1","unstructured":"J. Alakarhu, J. Niittylahti, Evaluating DRAM performance with various cache configurations, Proceedings of the 19th IASTED International Conference on Applied Informatics, Innsbruck, Austria, February 2001, pp. 100\u2013105."},{"key":"10.1016\/S0141-9331(02)00013-3_BIB2","unstructured":"J. Alakarhu, Rascas access, Datasheet, June 2001."},{"key":"10.1016\/S0141-9331(02)00013-3_BIB3","doi-asserted-by":"crossref","unstructured":"D. Burger, T.M. Austin, The Simple Scalar Tool Set Version 2.0, Technical report 1342, Computer Sciences Department, University of Wisconsin, June 1997.","DOI":"10.1145\/268806.268810"},{"issue":"2","key":"10.1016\/S0141-9331(02)00013-3_BIB4","doi-asserted-by":"crossref","first-page":"78","DOI":"10.1145\/232974.232983","article-title":"Memory bandwidth limitations of future microprocessors","volume":"27","author":"Burger","year":"1996","journal-title":"Computer-Architectures-News"},{"key":"10.1016\/S0141-9331(02)00013-3_BIB5","doi-asserted-by":"crossref","unstructured":"V. Cuppu, B. Jacob, B. Davis, T. Mudge, A performance comparison of contemporary DRAM architectures, Proceedings of the 26th International Symposium on Computer Architecture, Atlanta, GA, USA, May 1999, pp. 222\u2013233.","DOI":"10.1109\/ISCA.1999.765953"},{"key":"10.1016\/S0141-9331(02)00013-3_BIB6","series-title":"Test Driving Your Next Cache, Magazine of Intelligent Personal Systems","author":"Hill","year":"1989"},{"key":"10.1016\/S0141-9331(02)00013-3_BIB7","unstructured":"In Quest Market Research Inc., DDR vs. Rambus A Hands-on Performance Comparison, November 1999. Available at http:\/\/www.inqst.com\/articles\/ddrvrambus\/ddrvrambus.htm."},{"key":"10.1016\/S0141-9331(02)00013-3_BIB8","doi-asserted-by":"crossref","unstructured":"L. Wei-fen, S.K. Reinhardt, D. Burger, Reducing DRAM latencies with an integrated memory hierarchy design, Proceedings of the Seventh IEEE Symposium on High Performance Computer Architecture, Monterrey, Mexico, January 2001, pp. 301\u2013312.","DOI":"10.1109\/HPCA.2001.903272"},{"key":"10.1016\/S0141-9331(02)00013-3_BIB9","unstructured":"Micron, Inc., 128Mb: \u00d74, \u00d78, \u00d716, DDR SDRAM, April 2001."},{"key":"10.1016\/S0141-9331(02)00013-3_BIB10","unstructured":"Micron, Inc., 128Mb: \u00d74, \u00d78, \u00d716, SDRAM, May 2001."},{"issue":"2","key":"10.1016\/S0141-9331(02)00013-3_BIB11","doi-asserted-by":"crossref","first-page":"96","DOI":"10.1109\/43.681260","article-title":"Incorporating DRAM access modes into high-level synthesis","volume":"17","author":"Ranjan Panda","year":"1998","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"10.1016\/S0141-9331(02)00013-3_BIB12","unstructured":"Rambus, Inc., Direct RDRAM 128\/144-Mbit, June 2000."}],"container-title":["Microprocessors and Microsystems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933102000133?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933102000133?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,5,1]],"date-time":"2019-05-01T12:21:00Z","timestamp":1556713260000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0141933102000133"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,5]]},"references-count":12,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2002,5]]}},"alternative-id":["S0141933102000133"],"URL":"https:\/\/doi.org\/10.1016\/s0141-9331(02)00013-3","relation":{},"ISSN":["0141-9331"],"issn-type":[{"value":"0141-9331","type":"print"}],"subject":[],"published":{"date-parts":[[2002,5]]}}}