{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T11:59:58Z","timestamp":1649159998965},"reference-count":9,"publisher":"Elsevier BV","issue":"9","license":[{"start":{"date-parts":[[1997,5,1]],"date-time":"1997-05-01T00:00:00Z","timestamp":862444800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessors and Microsystems"],"published-print":{"date-parts":[[1997,5]]},"DOI":"10.1016\/s0141-9331(97)00004-5","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T22:50:06Z","timestamp":1027637406000},"page":"567-577","source":"Crossref","is-referenced-by-count":0,"title":["The hardware design of compute\/DRAM TRAMS"],"prefix":"10.1016","volume":"20","author":[{"given":"D.N.J.","family":"White","sequence":"first","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S0141-9331(97)00004-5_BIB1","unstructured":"The Transputer Applications Notebook, 72 TRN 205 00, Inmos, Bristol, 1989."},{"key":"10.1016\/S0141-9331(97)00004-5_BIB2","unstructured":"I. Graham, T. King, The Transputer Handbook, Prentice-Hall, Hemel Hempstead, 1990."},{"key":"10.1016\/S0141-9331(97)00004-5_BIB3","unstructured":"J. Hinton, A. Pinder, Transputer Hardware and System Design, Prentice-Hall, Hemel Hempstead, 1993."},{"key":"10.1016\/S0141-9331(97)00004-5_BIB4","unstructured":"IMS T805 Engineering Data, Inmos, Bristol, 1991."},{"key":"10.1016\/S0141-9331(97)00004-5_BIB5","unstructured":"The Transputer Databook, 72 TRN 203 01, Inmos, Bristol, 1989."},{"key":"10.1016\/S0141-9331(97)00004-5_BIB6","unstructured":"The Transputer Instruction Set\u2014A Compiler Writer's Guide, Prentice-Hall, Hemel Hempstead, 1988."},{"key":"10.1016\/S0141-9331(97)00004-5_BIB7","unstructured":"MOS Memory Data Book, Texas Instruments, Houston, 1993."},{"key":"10.1016\/S0141-9331(97)00004-5_BIB8","unstructured":"CUPL PLD\/FPGA Language Compiler, Logical Devices, Fort Lauderdale, 1991."},{"key":"10.1016\/S0141-9331(97)00004-5_BIB9","doi-asserted-by":"crossref","unstructured":"D.N.J. White, Interfacing Inmos links to the ISA bus, Microprocessors and Microsystems 19 (1995) 541\u2013551.","DOI":"10.1016\/0141-9331(96)89282-9"}],"container-title":["Microprocessors and Microsystems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933197000045?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933197000045?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,4,18]],"date-time":"2019-04-18T19:52:27Z","timestamp":1555617147000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0141933197000045"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,5]]},"references-count":9,"journal-issue":{"issue":"9","published-print":{"date-parts":[[1997,5]]}},"alternative-id":["S0141933197000045"],"URL":"https:\/\/doi.org\/10.1016\/s0141-9331(97)00004-5","relation":{},"ISSN":["0141-9331"],"issn-type":[{"value":"0141-9331","type":"print"}],"subject":[],"published":{"date-parts":[[1997,5]]}}}