{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T13:52:02Z","timestamp":1648907522471},"reference-count":13,"publisher":"Elsevier BV","issue":"1","license":[{"start":{"date-parts":[[1998,6,1]],"date-time":"1998-06-01T00:00:00Z","timestamp":896659200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Microprocessors and Microsystems"],"published-print":{"date-parts":[[1998,6]]},"DOI":"10.1016\/s0141-9331(98)00048-9","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T18:50:06Z","timestamp":1027623006000},"page":"49-60","source":"Crossref","is-referenced-by-count":0,"title":["A scalable register file architecture for superscalar processors"],"prefix":"10.1016","volume":"22","author":[{"given":"Steven","family":"Wallace","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nader","family":"Bagherzadeh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S0141-9331(98)00048-9_BIB1","series-title":"Superscalar Microprocessor Design","author":"Johnson","year":"1991"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB2","doi-asserted-by":"crossref","first-page":"28","DOI":"10.1109\/40.491460","article-title":"MIPS R10000 superscalar microprocessor","author":"Yeager","year":"1996","journal-title":"IEEE Micro"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB3","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1109\/MM.1994.363071","article-title":"The Power PC 604 RISC microprocessor","author":"Song","year":"1994","journal-title":"IEEE Micro"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB4","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1109\/40.491458","article-title":"Tuning the pentium pro microarchitecture","author":"Papworth","year":"1996","journal-title":"IEEE Micro"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB5","series-title":"25th Annual International Symposium on Microarchitecture","first-page":"292","article-title":"Partitioned register files for VLIWs: a preliminary analysis of tradeoffs","author":"Capitanio","year":"1992"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB6","series-title":"Second International Symposium on High-Performance Computer Architecture","first-page":"40","article-title":"Register file design considerations in dynamically scheduled processors","author":"Farkas","year":"1996"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB7","series-title":"23rd Annual International Symposium on Computer Architecture","article-title":"Exploiting choice: instruction fetch and issue on an implementable simultaneous multithreading processor","author":"Tullsen","year":"1996"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB8","doi-asserted-by":"crossref","first-page":"562","DOI":"10.1109\/12.4607","article-title":"Implementing precise interrupts in pipelined processors","volume":"C-37","author":"Smith","year":"1988","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB9","article-title":"An enhanced access and cycle time model for on-chip caches","author":"Wilton","year":"1994"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB10","doi-asserted-by":"crossref","DOI":"10.1145\/183019.183032","article-title":"Shade: a fast instruction-set simulator for execution profiling","author":"Cmelik","year":"1994","journal-title":"ACM SIGMETRICS"},{"issue":"4","key":"10.1016\/S0141-9331(98)00048-9_BIB11","doi-asserted-by":"crossref","first-page":"187","DOI":"10.1016\/0141-9331(95)91858-2","article-title":"Performance issues of a superscalar microprocessor","volume":"19","author":"Wallace","year":"1995","journal-title":"Microprocessors and Microsystems"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB12","series-title":"1995 International Conference on Computer Design","article-title":"Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor","author":"Wallace","year":"1995"},{"key":"10.1016\/S0141-9331(98)00048-9_BIB13","series-title":"28th Annual International Symposium on Microarchitecture","article-title":"The performance impact of incomplete bypassing in processor pipelines","author":"Ahuja","year":"1995"}],"container-title":["Microprocessors and Microsystems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933198000489?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0141933198000489?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,4,18]],"date-time":"2019-04-18T15:52:51Z","timestamp":1555602771000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0141933198000489"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,6]]},"references-count":13,"journal-issue":{"issue":"1","published-print":{"date-parts":[[1998,6]]}},"alternative-id":["S0141933198000489"],"URL":"https:\/\/doi.org\/10.1016\/s0141-9331(98)00048-9","relation":{},"ISSN":["0141-9331"],"issn-type":[{"value":"0141-9331","type":"print"}],"subject":[],"published":{"date-parts":[[1998,6]]}}}