{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T23:22:18Z","timestamp":1780356138623,"version":"3.54.1"},"reference-count":22,"publisher":"Elsevier BV","issue":"1-3","license":[{"start":{"date-parts":[[2002,11,1]],"date-time":"2002-11-01T00:00:00Z","timestamp":1036108800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2013,7,17]],"date-time":"2013-07-17T00:00:00Z","timestamp":1374019200000},"content-version":"vor","delay-in-days":3911,"URL":"https:\/\/www.elsevier.com\/open-access\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Discrete Applied Mathematics"],"published-print":{"date-parts":[[2002,11]]},"DOI":"10.1016\/s0166-218x(01)00339-0","type":"journal-article","created":{"date-parts":[[2002,10,14]],"date-time":"2002-10-14T15:12:20Z","timestamp":1034608340000},"page":"103-127","source":"Crossref","is-referenced-by-count":35,"title":["Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip"],"prefix":"10.1016","volume":"123","author":[{"given":"Christoph","family":"Albrecht","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Bernhard","family":"Korte","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"J\u00fcrgen","family":"Schietke","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jens","family":"Vygen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"78","reference":[{"key":"10.1016\/S0166-218X(01)00339-0_BIB1","unstructured":"U. B\u00fcnnagel, Effiziente Implementierung von Netzwerkalgorithmen, Diploma Thesis, University of Bonn, 1998 (in German)."},{"key":"10.1016\/S0166-218X(01)00339-0_BIB2","doi-asserted-by":"crossref","unstructured":"R.B. Deokar, S. Sapatnekar, A graph-theoretic approach to clock skew optimization, Proceedings of the IEEE International Symposium on Circuits and Systems, 1994, pp. 407\u2013410.","DOI":"10.1109\/ISCAS.1994.408825"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB3","doi-asserted-by":"crossref","first-page":"405","DOI":"10.1147\/rd.414.0405","article-title":"S\/390 parallel enterprise server generation3: a balanced system and cache structure","volume":"41","author":"Doettling","year":"1997","journal-title":"IBM J. Res. Dev."},{"key":"10.1016\/S0166-218X(01)00339-0_BIB4","doi-asserted-by":"crossref","first-page":"945","DOI":"10.1109\/12.55696","article-title":"Clock skew optimization","volume":"C-39","author":"Fishburn","year":"1990","journal-title":"Trans. Comput."},{"key":"10.1016\/S0166-218X(01)00339-0_BIB5","doi-asserted-by":"crossref","unstructured":"J.H. Huang, A.B. Kahng, C.-W.A. Tsao, On bounded-skew routing tree problem, Proceedings of the 32nd Design Automation Conference, 1995, pp. 508\u2013513.","DOI":"10.1109\/DAC.1995.250000"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB6","doi-asserted-by":"crossref","first-page":"309","DOI":"10.1016\/0012-365X(78)90011-0","article-title":"A characterization of the minimum mean cycle in a digraph","volume":"23","author":"Karp","year":"1978","journal-title":"Discrete Math."},{"key":"10.1016\/S0166-218X(01)00339-0_BIB7","doi-asserted-by":"crossref","first-page":"505","DOI":"10.1147\/rd.414.0505","article-title":"Standard-cell-based design methodology for high performance support chips","volume":"41","author":"Kick","year":"1997","journal-title":"IBM J. Res. Dev."},{"key":"10.1016\/S0166-218X(01)00339-0_BIB8","doi-asserted-by":"crossref","unstructured":"J. Koehl, U. Baur, T. Ludwig, B. Kick, T. Pflueger, A flat, timing-driven design system for a high-performance CMOS processor chipset, Proceedings of the Conference \u201cDesign, Automation and Test in Europe\u201d, 1998, pp. 312\u2013320.","DOI":"10.1109\/DATE.1998.655874"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB9","doi-asserted-by":"crossref","first-page":"535","DOI":"10.1109\/43.506140","article-title":"A timing analysis algorithm for circuits with level-sensitive latches","volume":"15","author":"Lee","year":"1996","journal-title":"IEEE Trans. Comput.-Aided Des. Integrated Circuits Systems"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB10","doi-asserted-by":"crossref","unstructured":"I. Lin, J.A. Ludwig, K. Eng, Analyzing cycle stealing on synchronous circuits with level-sensitive latches, Proceedings of the 29th ACM\/IEEE Design Automation Conference, 1992, pp. 393\u2013398.","DOI":"10.1109\/DAC.1992.227772"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB11","doi-asserted-by":"crossref","first-page":"852","DOI":"10.1145\/2157.322410","article-title":"Applying parallel computation algorithms in the design of serial algorithms","volume":"30","author":"Megiddo","year":"1983","journal-title":"J. Assoc. Comput. Machinery"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB12","unstructured":"K. Muuss, Clockskew Optimierung, Diploma Thesis, University of Bonn, 1994 (in German)."},{"key":"10.1016\/S0166-218X(01)00339-0_BIB13","doi-asserted-by":"crossref","unstructured":"J.L. Neves, E.G. Friedman, Optimal clock skew scheduling tolerant to process, variations, Proceedings of the 33rd Design Automation Conference, 1996, pp. 623\u2013628.","DOI":"10.1145\/240518.240636"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB14","doi-asserted-by":"crossref","unstructured":"K.A. Sakallah, T.N. Mudge, O.A. Olukotun, checkTc and minTc: timing verification and optimal clocking of synchronous digital circuits, Proceedings of the IEEE International Conference on Computer-Aided Design, 1990, pp. 552\u2013555.","DOI":"10.1109\/ICCAD.1990.129979"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB15","unstructured":"J. Schietke, Timing-Optimierung beim physikalischen Layout von nicht-hierarchischen Designs hochintegrierter Logikchips, Ph.D. Thesis, University of Bonn, 1999 (in German)."},{"key":"10.1016\/S0166-218X(01)00339-0_BIB16","doi-asserted-by":"crossref","first-page":"208","DOI":"10.1287\/moor.16.1.208","article-title":"Towers and cycle covers for max-balanced graph","volume":"16","author":"Schneider","year":"1991","journal-title":"Math. Oper. Res."},{"key":"10.1016\/S0166-218X(01)00339-0_BIB17","doi-asserted-by":"crossref","unstructured":"N. Shenoy, R.K. Brayton, Graph algorithms for clock schedule optimization, Proceedings of the IEEE International Conference on Computer-Aided Design, 1992, pp. 132\u2013136.","DOI":"10.1109\/ICCAD.1992.279401"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB18","doi-asserted-by":"crossref","unstructured":"T.G. Szymanski, Computing optimal clock schedules, Proceedings of the 29th ACM\/IEEE Design Automation Conference, 1992, pp. 399\u2013404.","DOI":"10.1109\/DAC.1992.227771"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB19","doi-asserted-by":"crossref","unstructured":"T.G. Szymanski, N. Shenoy, Verifying clock schedules, Proceedings of the IEEE International Conference on Computer-Aided Design, 1992, pp. 124\u2013131.","DOI":"10.1109\/ICCAD.1992.279387"},{"key":"10.1016\/S0166-218X(01)00339-0_BIB20","first-page":"205","article-title":"Exact zero skew","volume":"21","author":"Tsay","year":"1991","journal-title":"IEEE Trans. Comput.-Aided Des."},{"key":"10.1016\/S0166-218X(01)00339-0_BIB21","unstructured":"J. Vygen, Plazierung im VLSI-Design und ein zweidimensionales Zerlegungsproblem, Ph.D. Thesis, University of Bonn, 1996 (in German)."},{"key":"10.1016\/S0166-218X(01)00339-0_BIB22","doi-asserted-by":"crossref","first-page":"205","DOI":"10.1002\/net.3230210206","article-title":"Faster parametric shortest path and minimum balance algorithms","volume":"21","author":"Young","year":"1991","journal-title":"Networks"}],"container-title":["Discrete Applied Mathematics"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0166218X01003390?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0166218X01003390?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2024,12,3]],"date-time":"2024-12-03T17:22:42Z","timestamp":1733246562000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0166218X01003390"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,11]]},"references-count":22,"journal-issue":{"issue":"1-3","published-print":{"date-parts":[[2002,11]]}},"alternative-id":["S0166218X01003390"],"URL":"https:\/\/doi.org\/10.1016\/s0166-218x(01)00339-0","relation":{},"ISSN":["0166-218X"],"issn-type":[{"value":"0166-218X","type":"print"}],"subject":[],"published":{"date-parts":[[2002,11]]}}}