{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,24]],"date-time":"2026-01-24T19:11:46Z","timestamp":1769281906886,"version":"3.49.0"},"reference-count":118,"publisher":"Elsevier BV","issue":"7-8","license":[{"start":{"date-parts":[[2002,8,1]],"date-time":"2002-08-01T00:00:00Z","timestamp":1028160000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Parallel Computing"],"published-print":{"date-parts":[[2002,8]]},"DOI":"10.1016\/s0167-8191(02)00100-x","type":"journal-article","created":{"date-parts":[[2002,9,17]],"date-time":"2002-09-17T19:17:34Z","timestamp":1032290254000},"page":"1039-1078","source":"Crossref","is-referenced-by-count":36,"title":["Video compression with parallel processing"],"prefix":"10.1016","volume":"28","author":[{"given":"Ishfaq","family":"Ahmad","sequence":"first","affiliation":[]},{"given":"Yong","family":"He","sequence":"additional","affiliation":[]},{"given":"Ming L","family":"Liou","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"issue":"April\u2013June","key":"10.1016\/S0167-8191(02)00100-X_BIB1","doi-asserted-by":"crossref","first-page":"83","DOI":"10.1109\/4434.846198","article-title":"Gigantic clusters: Where are they and what are they doing","author":"Ahmad","year":"2000","journal-title":"IEEE Concurrency"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB2","unstructured":"I. Ahmad, S.M. Akramullah, M.L. Liou, M. Kafeel, A scalable off-line MPEG-2 encoder using a multiprocessor machine, Parallel Computing, in press"},{"issue":"3","key":"10.1016\/S0167-8191(02)00100-X_BIB3","doi-asserted-by":"crossref","first-page":"466","DOI":"10.1109\/30.320829","article-title":"MPEG-2 video codec using image compression DSP","volume":"40","author":"Akiyama","year":"1994","journal-title":"IEEE Transactions on Consumer Electronics"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB4","article-title":"A software based H.263 video encoder using network of workstations","volume":"vol. 3166","author":"Akramullah","year":"1997"},{"issue":"2","key":"10.1016\/S0167-8191(02)00100-X_BIB5","doi-asserted-by":"crossref","first-page":"129","DOI":"10.1006\/jpdc.1995.1133","article-title":"A data-parallel approach for real-time MPEG-2 video encoding","volume":"30","author":"Akramullah","year":"1995","journal-title":"Journal of Parallel and Distributed Computing"},{"issue":"4","key":"10.1016\/S0167-8191(02)00100-X_BIB6","doi-asserted-by":"crossref","first-page":"687","DOI":"10.1109\/76.611179","article-title":"Performance of a software-based MPEG-2 video encoder on parallel and distributed systems","volume":"7","author":"Akramullah","year":"1997","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB7","doi-asserted-by":"crossref","unstructured":"S.M. Akramullah, I. Ahmad, M.L. Liou, Parallel MPEG-2 encoder on ATM and ethernet-connected workstations, in: Proceedings of 4th International Conference on Parallel Computation, Salzburg, Austria, February 1999, pp. 572\u2013574","DOI":"10.1007\/3-540-49164-3_56"},{"issue":"8","key":"10.1016\/S0167-8191(02)00100-X_BIB8","doi-asserted-by":"crossref","first-page":"901","DOI":"10.1109\/76.937424","article-title":"Optimization of H.263 video encoding using a single processor computer: Performance trade-offs and benchmarking","volume":"11","author":"Akramullah","year":"2001","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB9","series-title":"International Conference on Consumer Electronics","first-page":"124","article-title":"A VLSI architecture for 2D mesh-based video object motion estimation","author":"Badawy","year":"2000"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB10","first-page":"1095","article-title":"A fast DCT-SQ scheme for images","author":"Arai","year":"1971","journal-title":"Transactions IEICE"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB11","series-title":"Proceedings of Tenth International Conference on VLSI Design","first-page":"247","article-title":"A parallel architecture for video compression","author":"Bhattacharjee","year":"1997"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB12","first-page":"780","article-title":"Scene adaptive rate control in a distributed parallel MPEG video encoder","volume":"vol. 2","author":"Bozoki","year":"1997"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB13","first-page":"977","article-title":"Efficient parallelization of an MPEG-2 codec on a TMS320C80 video processor","volume":"vol. 3","author":"Cantineau","year":"1998"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB14","first-page":"398","article-title":"A VLSI architecture design of VLC encoder for high data rate video\/image coding","volume":"vol. 4","author":"Chang","year":"1999"},{"issue":"4","key":"10.1016\/S0167-8191(02)00100-X_BIB15","doi-asserted-by":"crossref","first-page":"332","DOI":"10.1109\/76.465086","article-title":"Scalable array architecture design for full search block matching","volume":"5","author":"Chang","year":"1995","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"3","key":"10.1016\/S0167-8191(02)00100-X_BIB16","doi-asserted-by":"crossref","first-page":"623","DOI":"10.1109\/30.628685","article-title":"A high speed VLSI architecture of discrete wavelet transform for MPEG-4","volume":"43","author":"Chang","year":"1997","journal-title":"IEEE Transactions on Consumer Electronics"},{"issue":"6","key":"10.1016\/S0167-8191(02)00100-X_BIB17","doi-asserted-by":"crossref","first-page":"882","DOI":"10.1109\/76.785726","article-title":"Toward hardware building blocks for software-only real-time video processing: the movie approach","volume":"9","author":"Charot","year":"1999","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"5","key":"10.1016\/S0167-8191(02)00100-X_BIB18","doi-asserted-by":"crossref","first-page":"653","DOI":"10.1109\/82.673651","article-title":"A complete pipelined parallel CORDIC architecture for motion estimation","volume":"45","author":"Chen","year":"1998","journal-title":"IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing"},{"issue":"4","key":"10.1016\/S0167-8191(02)00100-X_BIB19","doi-asserted-by":"crossref","first-page":"378","DOI":"10.1109\/76.120779","article-title":"An efficient parallel motion estimation algorithm for digital image processing","volume":"1","author":"Chen","year":"1991","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB20","first-page":"102","article-title":"The impact of encoding algorithms on MPEG VLSI implementation","volume":"vol. 4","author":"Cheng","year":"1998"},{"issue":"1","key":"10.1016\/S0167-8191(02)00100-X_BIB21","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/76.134369","article-title":"Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems","volume":"2","author":"Chiu","year":"1992","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"2","key":"10.1016\/S0167-8191(02)00100-X_BIB22","doi-asserted-by":"crossref","first-page":"113","DOI":"10.1016\/0923-5965(95)00040-2","article-title":"High-speed moving picture coding using adaptively load balanced multiprocessor system","volume":"8","author":"Choi","year":"1996","journal-title":"Signal Processing: Image Communication"},{"issue":"22","key":"10.1016\/S0167-8191(02)00100-X_BIB23","doi-asserted-by":"crossref","first-page":"2109","DOI":"10.1049\/el:19981487","article-title":"Parallel H.263 video encoder in normal coding mode","volume":"34","author":"Cosmas","year":"1998","journal-title":"Electronics Letters"},{"issue":"7","key":"10.1016\/S0167-8191(02)00100-X_BIB24","doi-asserted-by":"crossref","first-page":"849","DOI":"10.1109\/76.735381","article-title":"H.263+: Video coding at low bit rates","volume":"8","author":"Cote","year":"1998","journal-title":"IEEE Transaction on Circuits and Systems for Video Technology"},{"issue":"5","key":"10.1016\/S0167-8191(02)00100-X_BIB25","doi-asserted-by":"crossref","first-page":"755","DOI":"10.1109\/5.664272","article-title":"On the applications of multimedia processing to communications","volume":"86","author":"Cox","year":"1998","journal-title":"Proceedings of the IEEE"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB26","series-title":"IEEE Ist Workshop on Multimedia Signal Processing","first-page":"343","article-title":"Block processing on multiprocessor DSPs for multimedia applications","author":"Cucchiara","year":"1997"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB27","series-title":"Proceedings of XII Brazilian Symposium on Computer Graphics and Image Processing","first-page":"215","article-title":"Parallelizing MPEG video encoding using multiprocessors","author":"Barbosa","year":"1999"},{"issue":"2","key":"10.1016\/S0167-8191(02)00100-X_BIB28","doi-asserted-by":"crossref","first-page":"85","DOI":"10.1109\/40.848475","article-title":"AltiVec extension to PowerPC accelerates media processing","volume":"20","author":"Diefendorff","year":"2000","journal-title":"IEEE Micro"},{"issue":"4\u20136","key":"10.1016\/S0167-8191(02)00100-X_BIB29","doi-asserted-by":"crossref","first-page":"489","DOI":"10.1016\/0923-5965(95)00003-8","article-title":"Speed-up trend analysis for H.261 and model-based image coding algorithms using a parallel-pipeline model","volume":"7","author":"Downton","year":"1995","journal-title":"Signal Processing: Image Communication"},{"issue":"1","key":"10.1016\/S0167-8191(02)00100-X_BIB30","doi-asserted-by":"crossref","first-page":"74","DOI":"10.1109\/76.486422","article-title":"A flexible parallel architecture adapted to block-matching motion-estimation algorithms","volume":"6","author":"Dutta","year":"1996","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"6","key":"10.1016\/S0167-8191(02)00100-X_BIB31","doi-asserted-by":"crossref","first-page":"1109","DOI":"10.1109\/5.687832","article-title":"Visual data compression for multimedia applications","volume":"86","author":"Ebrahimi","year":"1998","journal-title":"Proceedings of the IEEE"},{"issue":"11","key":"10.1016\/S0167-8191(02)00100-X_BIB32","doi-asserted-by":"crossref","first-page":"1744","DOI":"10.1109\/4.881222","article-title":"A parallel vector-quantization processor eliminating redundant calculations for real-time motion picture compression","volume":"35","author":"Nozawa","year":"2000","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB33","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1109\/40.888703","article-title":"Digital signal processor trends","author":"Frantz","year":"2000","journal-title":"IEEE Micro"},{"issue":"2","key":"10.1016\/S0167-8191(02)00100-X_BIB34","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1109\/79.826409","article-title":"Sub-word parallelism in digital signal processing","volume":"17","author":"Fridman","year":"2000","journal-title":"IEEE Signal Processing Magazine"},{"issue":"2","key":"10.1016\/S0167-8191(02)00100-X_BIB35","doi-asserted-by":"crossref","first-page":"159","DOI":"10.1109\/76.143415","article-title":"Parallel architecture for a pel-recursive motion estimation algorithm","volume":"2","author":"Frimout","year":"1992","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"4","key":"10.1016\/S0167-8191(02)00100-X_BIB36","doi-asserted-by":"crossref","first-page":"46","DOI":"10.1145\/103085.103090","article-title":"MPEG: a video compression standard for multimedia applications","volume":"34","author":"Le Gall","year":"1991","journal-title":"Communications of the ACM"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB37","series-title":"PVM: Parallel Virtual Machine\u2013\u2013A User's Guide and Tutorial for Networked Parallel Computing","author":"Geist","year":"1994"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB38","first-page":"908","article-title":"Three goals in designing VLSI architectures for video compression","volume":"vol. 2","author":"Gong","year":"1999"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB39","doi-asserted-by":"crossref","unstructured":"D. Gong, Y. He, Computation complexity analysis and VLSI architectures of shape coding for MPEG-4, in: Proceedings of SPIE, Visual Communications and Image Processing 2000, vol. 4067, 2000, pp. 1459\u20131470","DOI":"10.1117\/12.386564"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB40","unstructured":"K.L. Gong, L.A. Rowe, Parallel MPEG-1 video encoding, in: Picture Coding Symposium, California, September 1994"},{"issue":"3","key":"10.1016\/S0167-8191(02)00100-X_BIB41","doi-asserted-by":"crossref","first-page":"405","DOI":"10.1109\/5.747861","article-title":"Parallel computing in the commercial marketplace\u2013\u2013research and innovation at work","volume":"87","author":"Hagersten","year":"1999","journal-title":"Proceedings of the IEEE"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB42","series-title":"IEEE International Conference on Multimedia Computing and Systems","first-page":"204","article-title":"A study of concurrency in MPEG-4 video encoder","author":"Hamosfakidis","year":"1998"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB43","doi-asserted-by":"crossref","unstructured":"A. Hanami et al., A 165-GOPS motion estimation processor with adaptive dual-array architecture for high quality video-encoding applications, in: Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998, pp. 169\u2013172","DOI":"10.1109\/CICC.1998.694929"},{"issue":"7","key":"10.1016\/S0167-8191(02)00100-X_BIB44","doi-asserted-by":"crossref","first-page":"814","DOI":"10.1109\/76.735379","article-title":"Image and video coding\u2013\u2013emerging standards and beyond","volume":"8","author":"Haskell","year":"1998","journal-title":"IEEE Transaction on Circuits and Systems for Video Technology"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB45","series-title":"Digital Video: An Introduction to MPEG-2","author":"Haskell","year":"1997"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB46","first-page":"217","article-title":"Real-time interactive MPEG-4 system encoder using a cluster of workstations","volume":"12","author":"He","year":"1999","journal-title":"IEEE Transactions on Multimedia"},{"issue":"7","key":"10.1016\/S0167-8191(02)00100-X_BIB47","doi-asserted-by":"crossref","first-page":"909","DOI":"10.1109\/76.735385","article-title":"A software-based MPEG-4 video encoder using parallel processing","volume":"8","author":"He","year":"1998","journal-title":"IEEE Transaction on Circuits and Systems for Video Technology"},{"issue":"2","key":"10.1016\/S0167-8191(02)00100-X_BIB48","doi-asserted-by":"crossref","first-page":"169","DOI":"10.1109\/76.143416","article-title":"VLSI architecture for block-matching motion estimation algorithm","volume":"2","author":"Hsieh","year":"1992","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB49","series-title":"Scalable Parallel Computing, Technology, Architecture Programming","author":"Hwang","year":"1997"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB50","unstructured":"Intel orporation, Coarse-grain multithreading, Intel Application Note AP-802, Order no: 243636-002"},{"issue":"4","key":"10.1016\/S0167-8191(02)00100-X_BIB51","doi-asserted-by":"crossref","first-page":"407","DOI":"10.1109\/76.313135","article-title":"Parallel architectures for 3-step hierarchical search block-matching algorithm","volume":"4","author":"Jong","year":"1994","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB52","unstructured":"ITU-T experts group on very low bitrate visual telephony, ITU-T Recommendation H.263: Video coding for low bitrate communication, December 1995"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB53","unstructured":"ITU-T experts group on very bitrate visual telephony, ITU-T Recommendation H.263 version 2: Video coding for low bitrate communication, January 1998"},{"issue":"2","key":"10.1016\/S0167-8191(02)00100-X_BIB54","doi-asserted-by":"crossref","first-page":"161","DOI":"10.1109\/30.286411","article-title":"A real-time MPEG encoder using a programmable processor","volume":"40","author":"Kim","year":"1994","journal-title":"IEEE Transactions on Consumer Electronics"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB55","unstructured":"I.-K. Kim, J.-J. Cha, H.-J. Cho, A design of 2-D DCT\/IDCT for real-time video applications, in: 1999 International Conference on VLSI and CAD, 1999, pp. 557\u2013559"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB56","first-page":"551","article-title":"Scalable implementation of H.263 video encoder on a parallel DSP system","volume":"vol. 1","author":"Kolinummi","year":"2000"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB57","doi-asserted-by":"crossref","first-page":"16","DOI":"10.1109\/MSP.1998.664664","article-title":"VLIW architecture for media processing","volume":"152","author":"Konstantinides","year":"1998","journal-title":"IEEE Signal Processing Magazine"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB58","doi-asserted-by":"crossref","unstructured":"P. Kuhn et al., A flexible low-power VLSI architecture for MPEG-4 motion estimation, in: SPIE Conference on Visual Communications and Image Processing '99, vol. 3653, San Jose, CA, USA, January 1999, pp. 883\u2013894","DOI":"10.1117\/12.334740"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB59","series-title":"Algorithms, complexity analysis and VLSI architectures for MPEG-4 motion estimation","author":"Kuhn","year":"1999"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB60","doi-asserted-by":"crossref","first-page":"1203","DOI":"10.1109\/5.687835","article-title":"Multimedia processors","volume":"866","author":"Kuroda","year":"1998","journal-title":"Proceedings of the IEEE"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB61","doi-asserted-by":"crossref","unstructured":"D.-K. Yeung, A scalable MPEG-2 encoding system using the multithread architecture, M.Phil. Thesis, Hong Kong University of Science and Technology, September 2000","DOI":"10.14711\/thesis-b680862"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB62","first-page":"1243","article-title":"A new algorithm to compute the discrete cosine transform","author":"Lee","year":"1984","journal-title":"IEEE Transactions on Signal Processing"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB63","unstructured":"C. Lee, T. Yang, Y.F. Wang, Partitioning and scheduling for parallel image processing operations, in: 7th IEEE Symposium on Parallel and Distributed Processing, 1995, pp. 86\u201390"},{"issue":"2","key":"10.1016\/S0167-8191(02)00100-X_BIB64","first-page":"27","article-title":"Subword parallelism with MAX-2","volume":"17","author":"Lee","year":"2000","journal-title":"IEEE Signal Processing Magazine"},{"issue":"8","key":"10.1016\/S0167-8191(02)00100-X_BIB65","doi-asserted-by":"crossref","first-page":"1413","DOI":"10.1109\/76.889035","article-title":"Parallelization methodology for video coding\u2013\u2013an implementation on TMS320C80","volume":"10","author":"Leung","year":"2000","journal-title":"IEEE Transaction on Circuits and Systems for Video Technology"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB66","doi-asserted-by":"crossref","unstructured":"W. Lin, B. Tye, E. Ong, C. Xiong, T. Miki, S. Hotani, Systematic analysis and methodology of real-time DSP implementation for hybrid video coding, in: 1999 International Conference on Image Processing, vol. 3, 1999, pp. 847\u2013851","DOI":"10.1109\/ICIP.1999.817254"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB67","doi-asserted-by":"crossref","unstructured":"W. Lin et al., Real time H.263 video codec using parallel DSP, in: International Conference on Image Processing, vol. 2, 1997, pp. 586\u2013589","DOI":"10.1109\/ICIP.1997.638839"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB68","doi-asserted-by":"crossref","unstructured":"N. Ling, R. Advani, Architecture of a fast motion estimator for MPEG video coding, in: Second Symposium on Parallel Architectures, Algorithms, and Networks, 1996, pp. 473\u2013479","DOI":"10.1109\/ISPAN.1996.509028"},{"issue":"4","key":"10.1016\/S0167-8191(02)00100-X_BIB69","doi-asserted-by":"crossref","first-page":"59","DOI":"10.1145\/103085.103091","article-title":"Overview of the p\u00d764 kbps video coding standard","volume":"34","author":"Liou","year":"1991","journal-title":"Communications of the ACM"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB70","doi-asserted-by":"crossref","unstructured":"M.L. Liou, H. Fujiwara, VLSI implementation of a low bit-rate video codec, in: IEEE International Symposium on Circuits and Systems, 1991, pp. 180\u2013183","DOI":"10.1109\/ISCAS.1991.176303"},{"issue":"4","key":"10.1016\/S0167-8191(02)00100-X_BIB71","doi-asserted-by":"crossref","first-page":"1014","DOI":"10.1109\/30.477219","article-title":"The grand alliance HDTV video encoder","volume":"41","author":"Mailhot","year":"1995","journal-title":"IEEE Transactions on Consumer Electronics"},{"issue":"11","key":"10.1016\/S0167-8191(02)00100-X_BIB72","doi-asserted-by":"crossref","first-page":"3179","DOI":"10.1109\/78.796458","article-title":"A parallel implementation of the 2-D discrete wavelet transform without interprocessor communications","volume":"47","author":"Marino","year":"1999","journal-title":"IEEE Transactions on Signal Processing"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB73","doi-asserted-by":"crossref","unstructured":"M. Mattavelli, S. Brunetton, D. Mlynek, A parallel multimedia processor for macroblock based compression standards, in: International Conference on Image Processing, vol. 2, 1997, pp. 570\u2013573","DOI":"10.1109\/ICIP.1997.638835"},{"issue":"7","key":"10.1016\/S0167-8191(02)00100-X_BIB74","doi-asserted-by":"crossref","first-page":"1055","DOI":"10.1109\/5.390123","article-title":"VLSI for digital television","volume":"83","author":"Mlynek","year":"1995","journal-title":"Proceedings of the IEEE"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB75","unstructured":"MPEG-l video group, Information technology-coding of moving pictures and associated audio for digital storage media up to about 1.5 Mbit\/s: Part 2-Video, ISO\/lEC 11172-2, International Standard, 1993"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB76","unstructured":"MPEG-2 video group, Information technology-generic coding of moving pictures and associated audio: Part 2-Video, ISO\/lEC 13818-2, International Standard, 1995"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB77","unstructured":"MPEG-4 video group, Generic coding of audio-visual objects: Part 2-Visual, ISO\/IEC JTCI\/SC29\/WG11 N1902, FDIS of ISO\/lEC 14496-2, Atlantic City, November 1998"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB78","doi-asserted-by":"crossref","unstructured":"K. Nakamura, M. Ikeda, T. Yoshitome, T. Ogura, Global rate control scheme for MPEG-2 HDTV parallel encoding system, in: International Conference on Information Technology: Coding and Computing, 2000, pp. 195\u2013200","DOI":"10.1109\/ITCC.2000.844209"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB79","unstructured":"J. Nang et al., An effective parallelizing scheme of MPEG-1 video encoding on ethernet-connected workstations, in: Proceedings on Advances in Parallel and Distributed Computing, 1997, pp. 4\u201311"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB80","doi-asserted-by":"crossref","unstructured":"H. Nicolas, F. Jordan, Interactive optimization and massively parallel implementations of video compression algorithms, in: International Conference on Image Processing, vol. 1, 1996, pp. 229\u2013232","DOI":"10.1109\/ICIP.1996.559475"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB81","doi-asserted-by":"crossref","unstructured":"T. Nishitani, I. Tamitani, H. Harasaki, Programmable parallel processor for video processing, in: IEEE International Conference on Systems Engineering, 1989, pp. 169\u2013172","DOI":"10.1109\/ICSYSE.1989.48646"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB82","doi-asserted-by":"crossref","unstructured":"T. Olivares, P. Cuenca, F.J. Quiles, A. Garrido, Parallelization of the MPEG coding algorithm over a multicomputer. A proposal to evaluate its interconnection network, in: 1997 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, PACRIM, 10 Years Networking the Pacific Rim, 1987\u20131997, Part vol. 1, IEEE, New York, NY, USA, 1997, pp.113\u2013116","DOI":"10.1109\/PACRIM.1997.619914"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB83","doi-asserted-by":"crossref","unstructured":"S. Nogaki, A study on rate control method for MP@HL encoder with parallel encoder architecture using picture partitioning, in: 1999 International Conference on Image Processing, vol. 4, 1999, pp. 261\u2013265","DOI":"10.1109\/ICIP.1999.819591"},{"issue":"4","key":"10.1016\/S0167-8191(02)00100-X_BIB84","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/40.526924","article-title":"MMX technology extension to the intel architecture","volume":"16","author":"Peleg","year":"1996","journal-title":"IEEE Micro"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB85","series-title":"In search of clusters: The Ongoing Battle in Lowly Parallel Computing","author":"Pfister","year":"1998"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB86","doi-asserted-by":"crossref","unstructured":"A. Pirson, A Programmable Motion Estimation Processor for Full Search Block Matching, 1995 International Conference on Acoustics, Speech, and Signal Processing, vol. 5, 1995, pp. 3283\u20133286","DOI":"10.1109\/ICASSP.1995.479587"},{"issue":"7","key":"10.1016\/S0167-8191(02)00100-X_BIB87","doi-asserted-by":"crossref","first-page":"878","DOI":"10.1109\/76.735383","article-title":"VLSI implementations of image and video multimedia processing systems","volume":"8","author":"Pirsch","year":"1998","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"2","key":"10.1016\/S0167-8191(02)00100-X_BIB88","doi-asserted-by":"crossref","first-page":"1055","DOI":"10.1109\/5.364465","article-title":"VLSI architectures for video compression\u2013\u2013a survey","volume":"83","author":"Pirsch","year":"1995","journal-title":"Proceedings of the IEEE"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB89","doi-asserted-by":"crossref","unstructured":"A.M. Rassau, G. Alagoda, K. Eshraghian, Massively parallel wavelet based video codec for an intelligent-pixel multimedia communicator, in: Proceedings of the Fifth International Symposium on Signal Processing and Its Applications, vol. 2, 1999, pp. 793\u2013795","DOI":"10.1109\/ISSPA.1999.815791"},{"issue":"4","key":"10.1016\/S0167-8191(02)00100-X_BIB90","doi-asserted-by":"crossref","first-page":"1069","DOI":"10.1109\/30.477225","article-title":"Parallel programmable algorithm and architecture for real-time motion estimation of various video applications","volume":"41","author":"Saha","year":"1995","journal-title":"IEEE Transactions on Consumer Electronics"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB91","doi-asserted-by":"crossref","unstructured":"V. Sankar, S. Srinivasan, S.R. Rangarajan, Efficient implementation of MPEG video codec using dual processors, in: International Conference Digital Signal Processing, vol. 2, 1997, pp. 801\u2013804","DOI":"10.1109\/ICDSP.1997.628474"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB92","doi-asserted-by":"crossref","unstructured":"K. Shen, G.W. Cook, L.H. Jamieson, E.J. Delp, An overview of parallel processing approaches to image compression, in: Proceedings of the SPIE Conference on Image and Video Compression, vol. 2186, San Jose, California, February 1994, pp. 197\u2013208","DOI":"10.1117\/12.173920"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB93","doi-asserted-by":"crossref","unstructured":"K. Shen, E.J. Delp, A parallel implementation of an MPEG encoder: Faster than real-time, in: Proceedings of the SPIE Conference on Digital Video Compression: Algorithms and Technologies, San Jose, CA, 5\u201310 February, 1995, pp. 407\u2013418","DOI":"10.1117\/12.206377"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB94","doi-asserted-by":"crossref","unstructured":"K. Shen, E.J. Delp, A spatial-temporal parallel approach for real-time MPEG video compression, in: Proceedings of the 1996 International Conference on Parallel Processing, vol. 2, 1996, pp. 100\u2013107","DOI":"10.1109\/ICPP.1996.537388"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB95","doi-asserted-by":"crossref","first-page":"82","DOI":"10.1109\/79.618010","article-title":"MPEG digital video-coding standards","author":"Sikora","year":"1997","journal-title":"IEEE Signal Processing Magazine"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB96","doi-asserted-by":"crossref","unstructured":"T. Sikora, L. Chiariglione, MPEG-4 video and its potential for future multimedia services, in: Proceedings of 1997 IEEE International Symposium on Circuits and Systems, vol. 2, 1997, pp. 1468\u20131471","DOI":"10.1109\/ISCAS.1997.622195"},{"issue":"4","key":"10.1016\/S0167-8191(02)00100-X_BIB97","doi-asserted-by":"crossref","first-page":"610","DOI":"10.1109\/31.92893","article-title":"VLSI implementation of a 16\u00d716 discrete cosine transform","volume":"36","author":"Sun","year":"1989","journal-title":"IEEE Transactions on Circuits and Systems"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB98","series-title":"Workshop on VLSI Signal Processing","first-page":"119","article-title":"A SIMD DSP for real-time MPEG video encoding and decoding","author":"Tamitani","year":"1992"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB99","series-title":"Data Compression Conference","first-page":"552","article-title":"Parallel memories in video encoding","author":"Tanskanen","year":"1999"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB100","doi-asserted-by":"crossref","unstructured":"L. Thuyen, M. Glesner, Configurable VLSI-architectures for both standard DCT and shape-adaptive DCT in future MPEG-4 circuit implementations, in: The 2000 IEEE International Symposium on Circuits and Systems, vol. 2, 2000, pp. 461\u2013464","DOI":"10.1109\/ISCAS.2000.856364"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB101","doi-asserted-by":"crossref","unstructured":"P. Tiwari, E. Viscito, A parallel MPEG-2 video encoder with look-ahead rate control, in: IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 4, 1996, pp. 1994\u20131997","DOI":"10.1109\/ICASSP.1996.544845"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB102","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/40.526921","article-title":"VIS speeds new media processing","volume":"164","author":"Tremblay","year":"1996","journal-title":"IEEE Micro"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB103","doi-asserted-by":"crossref","unstructured":"B. Tye, DSP implementation of very low bit rate videoconferencing system, in: Proceedings of 1997 International Conference on Information, Communications and Signal Processing, vol. 3, 1997, pp. 1275\u20131278","DOI":"10.1109\/ICICS.1997.652192"},{"issue":"1","key":"10.1016\/S0167-8191(02)00100-X_BIB104","first-page":"56","article-title":"MPI: a standard message passing interface","volume":"12","author":"Walker","year":"1996","journal-title":"Supercomputer"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB105","doi-asserted-by":"crossref","unstructured":"S. Winograd, On computing the discrete fourier transform, IBM Research Report, 1976, RC-6291","DOI":"10.1073\/pnas.73.4.1005"},{"issue":"2","key":"10.1016\/S0167-8191(02)00100-X_BIB106","doi-asserted-by":"crossref","first-page":"207","DOI":"10.1109\/76.143420","article-title":"Architecture and implementation of a highly parallel single-chip video DSP","volume":"2","author":"Yamauchi","year":"1992","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB107","doi-asserted-by":"crossref","unstructured":"D.-K. Yeung, A scalable MPEG-2 encoding system using the multithread architecture, M.Phil. Thesis, Hong Kong University of Science and Technology, September 2000","DOI":"10.14711\/thesis-b680862"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB108","doi-asserted-by":"crossref","unstructured":"N.H.C. Yung, K.C. Chu, Fast and parallel video encoding by workload balancing, in: 1998 IEEE International Conference on Systems Man and Cybernetics, vol. 5, 1998, pp. 4642\u20134647","DOI":"10.1109\/ICSMC.1998.727584"},{"issue":"6","key":"10.1016\/S0167-8191(02)00100-X_BIB109","doi-asserted-by":"crossref","first-page":"833","DOI":"10.1109\/76.644063","article-title":"Optimization of fast block motion estimation algorithms","volume":"7","author":"Zeng","year":"1997","journal-title":"IEEE Transaction on Circuit and Systems for Video Technology"},{"issue":"5","key":"10.1016\/S0167-8191(02)00100-X_BIB110","doi-asserted-by":"crossref","first-page":"417","DOI":"10.1109\/76.473554","article-title":"VLSI architecture for a flexible block matching processor","volume":"5","author":"De Vos","year":"1995","journal-title":"IEEE Transaction on Circuits and Systems for Video Technology"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB111","doi-asserted-by":"crossref","unstructured":"A.A.J. Roach, A. Moini, VLSI archtietcure for motion estimation on a single-chip video camera, in: Proceedings of SPIE, vol. 4067, 2000, pp. 1441\u20131450","DOI":"10.1117\/12.386562"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB112","doi-asserted-by":"crossref","unstructured":"K.S. Prashant, V.J. Mathews, A massively parallel algorithm for vector quantization, in: Proceedings of Data Compression Conference, 1995, pp. 499","DOI":"10.1109\/DCC.1995.515604"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB113","doi-asserted-by":"crossref","unstructured":"K. Kobayashi et al., A functional memory type parallel processor for vector quantization, in: Proceedings of the Asia and South Pacific Design Automation Conference, 1997, pp. 665\u2013666","DOI":"10.1109\/ASPDAC.1997.600354"},{"issue":"6","key":"10.1016\/S0167-8191(02)00100-X_BIB114","doi-asserted-by":"crossref","first-page":"467","DOI":"10.1109\/82.502319","article-title":"Flexible VLSI architecture of motion estimation for video image compression","volume":"43","author":"Nam","year":"1996","journal-title":"IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing"},{"issue":"5","key":"10.1016\/S0167-8191(02)00100-X_BIB115","doi-asserted-by":"crossref","first-page":"819","DOI":"10.1109\/76.633505","article-title":"Design of fast motion estimation algorithm based on hardware consideration","volume":"7","author":"He","year":"1997","journal-title":"IEEE Transaction on Circuits and Systems for Video Technology"},{"issue":"5","key":"10.1016\/S0167-8191(02)00100-X_BIB116","doi-asserted-by":"crossref","first-page":"669","DOI":"10.1109\/76.856445","article-title":"Low-power VLSI design for motion estimation using adaptive pixel truncation","volume":"10","author":"He","year":"2000","journal-title":"IEEE Transaction on Circuits and Systems for Video Technology"},{"issue":"1","key":"10.1016\/S0167-8191(02)00100-X_BIB117","doi-asserted-by":"crossref","first-page":"91","DOI":"10.1109\/76.894289","article-title":"Spatial and temporal data parallelization of the H.261 video coding algorithm","volume":"11","author":"Yung","year":"2001","journal-title":"IEEE Transaction on Circuits and Systems on Video Technology"},{"key":"10.1016\/S0167-8191(02)00100-X_BIB118","doi-asserted-by":"crossref","unstructured":"O. Lehtoranta, T. Hamalainen, J. Saarinen, Parallel implementation of H.263 encoder for CIF-sized images on quad DSP system, in: IEEE International Symposium on Circuits and Systems, ISCAS2001, vol. 2, 2001, pp. 209\u2013212","DOI":"10.1109\/ISCAS.2001.921044"}],"container-title":["Parallel Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S016781910200100X?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S016781910200100X?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2024,12,10]],"date-time":"2024-12-10T00:34:11Z","timestamp":1733790851000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S016781910200100X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,8]]},"references-count":118,"journal-issue":{"issue":"7-8","published-print":{"date-parts":[[2002,8]]}},"alternative-id":["S016781910200100X"],"URL":"https:\/\/doi.org\/10.1016\/s0167-8191(02)00100-x","relation":{},"ISSN":["0167-8191"],"issn-type":[{"value":"0167-8191","type":"print"}],"subject":[],"published":{"date-parts":[[2002,8]]}}}