{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T09:40:18Z","timestamp":1759138818584,"version":"3.44.0"},"reference-count":24,"publisher":"Elsevier BV","issue":"2","license":[{"start":{"date-parts":[[2003,8,1]],"date-time":"2003-08-01T00:00:00Z","timestamp":1059696000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[2003,8,1]],"date-time":"2003-08-01T00:00:00Z","timestamp":1059696000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[2003,8]]},"DOI":"10.1016\/s0167-9260(03)00029-4","type":"journal-article","created":{"date-parts":[[2003,6,30]],"date-time":"2003-06-30T09:57:08Z","timestamp":1056967028000},"page":"69-84","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":9,"title":["An efficient hierarchical timing-driven Steiner tree algorithm for global routing"],"prefix":"10.1016","volume":"35","author":[{"given":"Jingyu","family":"Xu","sequence":"first","affiliation":[]},{"given":"Xianlong","family":"Hong","sequence":"additional","affiliation":[]},{"given":"Tong","family":"Jing","sequence":"additional","affiliation":[]},{"given":"Yici","family":"Cai","sequence":"additional","affiliation":[]},{"given":"Jun","family":"Gu","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S0167-9260(03)00029-4_BIB1","unstructured":"H.B. Bakoglu, Circuits Interconnections and Packaging for VLSI, Addison-Wesley, Reading, MA, 1990, pp. 195\u2013198."},{"year":"1998","series-title":"The Theories and Algorithms for VLSI Layout Design","author":"Hong","key":"10.1016\/S0167-9260(03)00029-4_BIB2"},{"key":"10.1016\/S0167-9260(03)00029-4_BIB3","doi-asserted-by":"crossref","unstructured":"Janson Cong, Kwok-Shing Leung, Optimal wiresizing under Elmore delay model, IEEE Trans. CAD 14 (3) (1995) 321\u2013336.","DOI":"10.1109\/43.365123"},{"key":"10.1016\/S0167-9260(03)00029-4_BIB4","doi-asserted-by":"crossref","unstructured":"Janson Cong, Lei He, Optimal wiresizing for interconnects with multiple sources, ACM Trans. Design Automat. Electron. Systems 1 (1\u20134) (1996) 478\u2013511.","DOI":"10.1145\/238997.239018"},{"key":"10.1016\/S0167-9260(03)00029-4_BIB5","doi-asserted-by":"crossref","unstructured":"J. Lillis, Chung-Kuan Cheng, Ting-Ting, Y. Lin, et al., New performance driven routing techniques with explicit area\/delay tradeoff and simultaneous wire sizing, Proceedings of the 33rd Design Automation Conference (DAC), Las Vegas, Nevada, 1996.","DOI":"10.1145\/240518.240594"},{"issue":"9","key":"10.1016\/S0167-9260(03)00029-4_BIB6","doi-asserted-by":"crossref","first-page":"1297","DOI":"10.1109\/43.784121","article-title":"An efficient and optimal algorithm for simultaneous buffer and wire sizing","volume":"18","author":"Chu","year":"1999","journal-title":"IEEE Trans. CAD"},{"key":"10.1016\/S0167-9260(03)00029-4_BIB7","doi-asserted-by":"crossref","unstructured":"Jiang Hu, S.S. Sapatnekar, Algorithm for non-Hanan-based optimization for VLSI interconnect under higher-order AWE model, IEEE Trans. CAD 19 (4) (2000) 446\u2013458.","DOI":"10.1109\/43.838994"},{"key":"10.1016\/S0167-9260(03)00029-4_BIB8","doi-asserted-by":"crossref","unstructured":"John Lillis, Chung-Kuan Cheng, Timing optimization for multisource nets: characterization and optimal repeater insertion, IEEE Trans. CAD 18 (3) (1999) 322\u2013331.","DOI":"10.1109\/43.748162"},{"key":"10.1016\/S0167-9260(03)00029-4_BIB9","doi-asserted-by":"crossref","unstructured":"S. Prasitjutrakul, W.J. Kubitz, A timing-driven global router for custom chip design, ICCAD\u201990, Santa Barbara, CA, USA, 1990, pp. 48\u201351.","DOI":"10.1109\/ICCAD.1990.129837"},{"issue":"2","key":"10.1016\/S0167-9260(03)00029-4_BIB10","first-page":"120","article-title":"Provably good performance-driven global routing","volume":"10","author":"Cong","year":"1991","journal-title":"IEEE Trans. CAD"},{"key":"10.1016\/S0167-9260(03)00029-4_BIB11","doi-asserted-by":"crossref","unstructured":"X.L. Hong, T.X. Xue, E.S. Kuh, C.K. Cheng, et al., Performance-driven Steiner tree algorithms for global routing, Proceedings of the 30th Design Automation Conference (DAC), Dallas, Texas, 1993, pp. 177\u2013181.","DOI":"10.1145\/157485.164658"},{"issue":"4","key":"10.1016\/S0167-9260(03)00029-4_BIB12","first-page":"266","article-title":"A performance-driven Steiner tree algorithm for global routing","volume":"18","author":"Hong","year":"1995","journal-title":"Chin. J. Comput."},{"issue":"3","key":"10.1016\/S0167-9260(03)00029-4_BIB13","first-page":"218","article-title":"A performance-driven Steiner tree algorithm using constructed force directed approach for global routing","volume":"16","author":"Hong","year":"1995","journal-title":"Chin. J. Semicond."},{"issue":"1","key":"10.1016\/S0167-9260(03)00029-4_BIB14","first-page":"41","article-title":"Timing-driven Steiner tree algorithm based on Sakurai model","volume":"20","author":"Bao","year":"1999","journal-title":"Chin. J. Semicond."},{"key":"10.1016\/S0167-9260(03)00029-4_BIB15","doi-asserted-by":"crossref","unstructured":"C. Alpert, et al., Buffered Steiner trees for difficult instances, ISPD\u201901, Sonoma, CA, USA, 2001, pp. 4\u20139.","DOI":"10.1145\/369691.369699"},{"key":"10.1016\/S0167-9260(03)00029-4_BIB16","doi-asserted-by":"crossref","unstructured":"Xiaoping Tang, Ruiqi Tian, Hua Xiang, D.F. Wong, A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints, ICCAD\u201901, San Jose, USA, 2001, pp. 49\u201356.","DOI":"10.1109\/ICCAD.2001.968597"},{"key":"10.1016\/S0167-9260(03)00029-4_BIB17","doi-asserted-by":"crossref","unstructured":"A. Vittal, M. Marek-Sadowska, Minimum delay interconnect design using alphabetic trees, Proceeding of the ACM\/IEEE Design Automation Conference, San Diego, USA, 1994, pp. 392\u2013396.","DOI":"10.1145\/196244.196432"},{"issue":"9","key":"10.1016\/S0167-9260(03)00029-4_BIB18","doi-asserted-by":"crossref","first-page":"1095","DOI":"10.1109\/43.159995","article-title":"Hierarchical Steiner tree construction in uniform orientations","volume":"11","author":"Sarrafzadeh","year":"1992","journal-title":"IEEE Trans. CAD"},{"issue":"4","key":"10.1016\/S0167-9260(03)00029-4_BIB19","doi-asserted-by":"crossref","first-page":"418","DOI":"10.1109\/JSSC.1983.1051966","article-title":"Approxiamation of wiring delay in MOSFET LSI","volume":"18","author":"Sakurai","year":"1983","journal-title":"IEEE J. Solid-State Circuits (SSC)"},{"issue":"1","key":"10.1016\/S0167-9260(03)00029-4_BIB20","doi-asserted-by":"crossref","first-page":"55","DOI":"10.1063\/1.1697872","article-title":"The transient response of lumped linear networks with particular regard to wideband amplifiers","volume":"19","author":"Elmore","year":"1948","journal-title":"J. Appl. Phys."},{"key":"10.1016\/S0167-9260(03)00029-4_BIB21","doi-asserted-by":"crossref","unstructured":"R. Gupta, B. Krauter, B. Tutuianu, et al., The elmore delay as a bound for RC trees with generalized input signals, Proceedings of the 32nd Design Automation Conference (DAC), San Francisco, CA, 1995, pp. 364\u2013369.","DOI":"10.1109\/DAC.1995.249974"},{"issue":"4","key":"10.1016\/S0167-9260(03)00029-4_BIB22","doi-asserted-by":"crossref","first-page":"446","DOI":"10.1109\/43.838994","article-title":"Algorithm for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model","volume":"19","author":"Hu","year":"2000","journal-title":"IEEE Trans. CAD"},{"key":"10.1016\/S0167-9260(03)00029-4_BIB23","doi-asserted-by":"crossref","first-page":"195","DOI":"10.1002\/net.3230010302","article-title":"The Steiner problem in graph","volume":"1","author":"Dreyfus","year":"1972","journal-title":"Networks."},{"year":"1999","series-title":"The ABC of Digital CMOS VLSI Analysis and Design","author":"Gan","key":"10.1016\/S0167-9260(03)00029-4_BIB24"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926003000294?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926003000294?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T09:11:47Z","timestamp":1759137107000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0167926003000294"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,8]]},"references-count":24,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2003,8]]}},"alternative-id":["S0167926003000294"],"URL":"https:\/\/doi.org\/10.1016\/s0167-9260(03)00029-4","relation":{},"ISSN":["0167-9260"],"issn-type":[{"type":"print","value":"0167-9260"}],"subject":[],"published":{"date-parts":[[2003,8]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"An efficient hierarchical timing-driven Steiner tree algorithm for global routing","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/S0167-9260(03)00029-4","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 2003 Elsevier B.V. All rights reserved.","name":"copyright","label":"Copyright"}]}}