{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T09:40:01Z","timestamp":1759138801019,"version":"3.44.0"},"reference-count":18,"publisher":"Elsevier BV","issue":"2","license":[{"start":{"date-parts":[[1986,6,1]],"date-time":"1986-06-01T00:00:00Z","timestamp":517968000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1986,6,1]],"date-time":"1986-06-01T00:00:00Z","timestamp":517968000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[1986,6]]},"DOI":"10.1016\/s0167-9260(86)80005-0","type":"journal-article","created":{"date-parts":[[2004,11,13]],"date-time":"2004-11-13T11:59:08Z","timestamp":1100347148000},"page":"155-173","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":1,"title":["On minimizing memory in systolic arrays for the dynamic time warping algorithm"],"prefix":"10.1016","volume":"4","author":[{"given":"E.","family":"Dijkstra","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.","family":"Piguet","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"year":"1980","series-title":"Introduction to VLSI Systems","author":"Mead","key":"10.1016\/S0167-9260(86)80005-0_bib1"},{"article-title":"Area Efficient VLSI Computation","year":"1983","author":"Leiserson","key":"10.1016\/S0167-9260(86)80005-0_bib2"},{"key":"10.1016\/S0167-9260(86)80005-0_bib3","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/MC.1982.1653825","article-title":"Why systolic architectures?","volume":"15","author":"Kung","year":"1982","journal-title":"IEEE Computer"},{"key":"10.1016\/S0167-9260(86)80005-0_bib4","unstructured":"Spaanenburg, L., Technical University of Twente, The Netherlands, private communication."},{"issue":"1","key":"10.1016\/S0167-9260(86)80005-0_bib5","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1109\/TASSP.1978.1163055","article-title":"Dynamic programming algorithm optimization for spoken word recognition","volume":"ASSP-26","author":"Sakoe","year":"1978","journal-title":"IEEE Trans. Acoust., Speech and Signal Process."},{"key":"10.1016\/S0167-9260(86)80005-0_bib6","unstructured":"Deczky, A.G., Recognition of isolated words for small vocabularies, description of algorithms, Rapport No. 46 EC 02 002, Institut de Microtechnique de l'Universit\u00e9 de Neuch\u00e2tel."},{"key":"10.1016\/S0167-9260(86)80005-0_bib7","series-title":"Proc. Eight International Symp. on Computer Architecture","first-page":"12","article-title":"An integrated multiprocessor array for time warp pattern matching","author":"Ackland","year":"1981"},{"key":"10.1016\/S0167-9260(86)80005-0_bib8","series-title":"VLSI '81, Conference Proceedings","article-title":"Bit-serial VLSI architecture methodology","author":"Lyon","year":"1981"},{"key":"10.1016\/S0167-9260(86)80005-0_bib9","unstructured":"Strader, N.R., VLSI bit-serial architectures for digital signal processing, ICASSP'83, Boston."},{"key":"10.1016\/S0167-9260(86)80005-0_bib10","article-title":"R\u00e9seaux systoliques pour l'algorithme DTW en reconnaissance de mots isol\u00e9s, Centre Electronique Horloger S.A., Neuch\u00e2tel","author":"Dijkstra","year":"1984","journal-title":"Internal Tech. Report No. 291"},{"issue":"3","key":"10.1016\/S0167-9260(86)80005-0_bib11","doi-asserted-by":"crossref","first-page":"425","DOI":"10.1109\/JSSC.1984.1052158","article-title":"A metal-oriented layout structure for CMOS logic","volume":"SC-19","author":"Piguet","year":"1984","journal-title":"IEEE J. Solid-State Circ."},{"key":"10.1016\/S0167-9260(86)80005-0_bib12","doi-asserted-by":"crossref","first-page":"335","DOI":"10.1016\/S0167-9260(83)80006-6","article-title":"Design methodology for full custom CMOS microcomputers","volume":"1","author":"Piguet","year":"1983","journal-title":"Integration, the VLSI Journal"},{"issue":"11","key":"10.1016\/S0167-9260(86)80005-0_bib13","doi-asserted-by":"crossref","first-page":"1070","DOI":"10.1109\/TCS.1981.1084930","article-title":"Design for autonomous test","volume":"CAS-28","author":"McCluskey","year":"1981","journal-title":"IEEE Trans. Circ. Systems"},{"issue":"3","key":"10.1016\/S0167-9260(86)80005-0_bib14","doi-asserted-by":"crossref","first-page":"481","DOI":"10.1109\/JSSC.1982.1051763","article-title":"The impact of testing on VLSI design methods","volume":"SC-17","author":"Rene Segers","year":"1982","journal-title":"IEEE J. Solid-State Circ."},{"issue":"1","key":"10.1016\/S0167-9260(86)80005-0_bib15","doi-asserted-by":"crossref","first-page":"2","DOI":"10.1109\/TC.1982.1675879","article-title":"Design for testability-a survey","volume":"C-31","author":"Williams","year":"1982","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0167-9260(86)80005-0_bib16","series-title":"Dig. 1979 Test Conf.","first-page":"37","article-title":"Built in logic observation techniques","author":"Koenemann","year":"1979"},{"key":"10.1016\/S0167-9260(86)80005-0_bib17","doi-asserted-by":"crossref","first-page":"510","DOI":"10.1109\/TC.1980.1675610","article-title":"Measure of the effectiveness of fault signature analysis","volume":"C-29","author":"Smith","year":"1980","journal-title":"IEEE Trans. Comput."},{"issue":"2","key":"10.1016\/S0167-9260(86)80005-0_bib18","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1109\/MDT.1984.5005609","article-title":"Design for testability and self testing approaches for bit-serial signal processors","volume":"1","author":"Kanopoulos","year":"1984","journal-title":"IEEE Design Test Comput."}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926086800050?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926086800050?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T09:12:00Z","timestamp":1759137120000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0167926086800050"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1986,6]]},"references-count":18,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1986,6]]}},"alternative-id":["S0167926086800050"],"URL":"https:\/\/doi.org\/10.1016\/s0167-9260(86)80005-0","relation":{},"ISSN":["0167-9260"],"issn-type":[{"type":"print","value":"0167-9260"}],"subject":[],"published":{"date-parts":[[1986,6]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"On minimizing memory in systolic arrays for the dynamic time warping algorithm","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/S0167-9260(86)80005-0","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1986 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}]}}