{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,30]],"date-time":"2025-09-30T00:06:34Z","timestamp":1759190794973,"version":"3.44.0"},"reference-count":10,"publisher":"Elsevier BV","issue":"2","license":[{"start":{"date-parts":[[1997,11,1]],"date-time":"1997-11-01T00:00:00Z","timestamp":878342400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1997,11,1]],"date-time":"1997-11-01T00:00:00Z","timestamp":878342400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[1997,11]]},"DOI":"10.1016\/s0167-9260(97)00020-5","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T15:24:04Z","timestamp":1027610644000},"page":"157-170","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"title":["Serial diagnostic fault simulation for synchronous sequential circuits"],"prefix":"10.1016","volume":"23","author":[{"given":"Shung-Chih","family":"Chen","sequence":"first","affiliation":[]},{"given":"Jer Min","family":"Jou","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S0167-9260(97)00020-5_bib1","series-title":"Proc. Int. Test Conf.","first-page":"52","article-title":"A diagnostic test pattern generation algorithm","author":"Camurati","year":"1990"},{"key":"10.1016\/S0167-9260(97)00020-5_bib2","series-title":"Proc. 29th Design Automation Conf.","first-page":"347","article-title":"Exact evaluation of diagnostic test resolution","author":"Kubiak","year":"1992"},{"key":"10.1016\/S0167-9260(97)00020-5_bib3","doi-asserted-by":"crossref","first-page":"198","DOI":"10.1109\/43.124398","article-title":"PROOFS: a fast, memory-efficient sequential circuit fault simulator","author":"Niermann","year":"1992","journal-title":"IEEE Trans. CAD"},{"key":"10.1016\/S0167-9260(97)00020-5_bib4","series-title":"Proc. Int. Test Conf.","first-page":"178","article-title":"Diagnostic fault simulation of sequential circuits","author":"Rudnick","year":"1992"},{"key":"10.1016\/S0167-9260(97)00020-5_bib5","series-title":"Int. Symp. of Circuits and Systems","first-page":"1929","article-title":"Combinational profiles of sequential benchmark circuits","author":"Brglez","year":"1989"},{"key":"10.1016\/S0167-9260(97)00020-5_bib6","series-title":"IEEE Asia-Pacific Conf. on Circuits and Systems","first-page":"466","article-title":"A new fault simulator for large synchronous sequential circuits","author":"Jou","year":"1994"},{"key":"10.1016\/S0167-9260(97)00020-5_bib7","series-title":"29th Design Automation Conf.","first-page":"336","article-title":"HOPE: an efficient parallel fault simulator for synchronous sequential circuits","author":"Lee","year":"1992"},{"key":"10.1016\/S0167-9260(97)00020-5_bib8","series-title":"Int. Conf. on Computer-Aided Design","first-page":"5","article-title":"New methods of improving parallel fault simulation in synchronous sequential circuits","author":"Lee","year":"1993"},{"key":"10.1016\/S0167-9260(97)00020-5_bib9","series-title":"Int. Symp. of Circuits and Systems","first-page":"1938","article-title":"Sequential circuit test generator (STG) benchmark results","author":"Cheng","year":"1989"},{"key":"10.1016\/S0167-9260(97)00020-5_bib10","series-title":"Proc. European Design Automation Conf.","first-page":"214","article-title":"HITEC: a test generation package for sequential circuits","author":"Niermann","year":"1991"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926097000205?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926097000205?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T09:12:13Z","timestamp":1759137133000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0167926097000205"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,11]]},"references-count":10,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1997,11]]}},"alternative-id":["S0167926097000205"],"URL":"https:\/\/doi.org\/10.1016\/s0167-9260(97)00020-5","relation":{},"ISSN":["0167-9260"],"issn-type":[{"type":"print","value":"0167-9260"}],"subject":[],"published":{"date-parts":[[1997,11]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Serial diagnostic fault simulation for synchronous sequential circuits","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/S0167-9260(97)00020-5","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1997 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}]}}