{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,30]],"date-time":"2025-09-30T00:06:32Z","timestamp":1759190792537,"version":"3.44.0"},"reference-count":10,"publisher":"Elsevier BV","issue":"2","license":[{"start":{"date-parts":[[1997,12,1]],"date-time":"1997-12-01T00:00:00Z","timestamp":880934400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1997,12,1]],"date-time":"1997-12-01T00:00:00Z","timestamp":880934400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[1997,12]]},"DOI":"10.1016\/s0167-9260(97)00028-x","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T14:27:12Z","timestamp":1027607232000},"page":"119-133","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":0,"title":["Overcoming chip-to-chip delays and clock skews"],"prefix":"10.1016","volume":"24","author":[{"given":"Guy","family":"Even","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ami","family":"Litman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S0167-9260(97)00028-X_BIB1","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/MC.1982.1653825","article-title":"Why systolic architectures?","author":"Kung","year":"1982","journal-title":"IEEE Comput. Mag."},{"article-title":"Area-efficient VLSI computation","year":"1983","author":"Leiserson","key":"10.1016\/S0167-9260(97)00028-X_BIB2"},{"key":"10.1016\/S0167-9260(97)00028-X_BIB3_1","series-title":"Proc. 22nd Annual Symp. on Foundations of Computer Science","first-page":"23","article-title":"Optimizing synchronous systems","author":"Leiserson","year":"1981"},{"key":"10.1016\/S0167-9260(97)00028-X_BIB3_2","first-page":"41","volume":"1","author":"Leiserson","year":"1983","journal-title":"J. VLSI Comput. Systems"},{"key":"10.1016\/S0167-9260(97)00028-X_BIB4_1","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1007\/BF01187090","article-title":"On the capabilities of systolic systems","volume":"27","author":"Even","year":"1994","journal-title":"Math. Systems Theory"},{"year":"1991","series-title":"A preliminary version of the paper appeared in the Proceedings of the 3rd ACM Symp. on Parallel Algorithms and Architectures","author":"Even","key":"10.1016\/S0167-9260(97)00028-X_BIB4_2"},{"key":"10.1016\/S0167-9260(97)00028-X_BIB5","doi-asserted-by":"crossref","first-page":"123","DOI":"10.1016\/0167-9260(95)00021-6","article-title":"The Retiming Lemma: A simple proof and applications, Integration","volume":"20","author":"Even","year":"1996","journal-title":"VLSI J."},{"issue":"1","key":"10.1016\/S0167-9260(97)00028-X_BIB6","doi-asserted-by":"crossref","first-page":"5","DOI":"10.1007\/BF01759032","article-title":"Retiming synchronous circuitry","volume":"6","author":"Leiserson","year":"1991","journal-title":"Algorithmica"},{"key":"10.1016\/S0167-9260(97)00028-X_BIB7_1","unstructured":"M.C. Papaefthymiou, Understanding retiming through maximum average-delay cycles, Mathematical Systems Theory, to appear."},{"year":"1991","series-title":"A preliminary version of the paper appeared in the Proc. of the 3rd ACM Symp. on Parallel Algorithms and Architectures","author":"Papaefthymiou","key":"10.1016\/S0167-9260(97)00028-X_BIB7_2"}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S016792609700028X?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S016792609700028X?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T09:09:18Z","timestamp":1759136958000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S016792609700028X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,12]]},"references-count":10,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1997,12]]}},"alternative-id":["S016792609700028X"],"URL":"https:\/\/doi.org\/10.1016\/s0167-9260(97)00028-x","relation":{},"ISSN":["0167-9260"],"issn-type":[{"type":"print","value":"0167-9260"}],"subject":[],"published":{"date-parts":[[1997,12]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Overcoming chip-to-chip delays and clock skews","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/S0167-9260(97)00028-X","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1997 Published by Elsevier B.V.","name":"copyright","label":"Copyright"}]}}