{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:06:35Z","timestamp":1774631195518,"version":"3.50.1"},"reference-count":15,"publisher":"Elsevier BV","issue":"2","license":[{"start":{"date-parts":[[1999,7,1]],"date-time":"1999-07-01T00:00:00Z","timestamp":930787200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1999,7,1]],"date-time":"1999-07-01T00:00:00Z","timestamp":930787200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Integration"],"published-print":{"date-parts":[[1999,7]]},"DOI":"10.1016\/s0167-9260(99)00002-4","type":"journal-article","created":{"date-parts":[[2003,1,30]],"date-time":"2003-01-30T15:45:15Z","timestamp":1043941515000},"page":"113-129","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":22,"title":["Generating new benchmark designs using a multi-terminal net model"],"prefix":"10.1016","volume":"27","author":[{"given":"Dirk","family":"Stroobandt","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jo","family":"Depreitere","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jan Van","family":"Campenhout","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S0167-9260(99)00002-4_BIB1","doi-asserted-by":"crossref","unstructured":"J. Darnauer, W.W. Dai, A method for generating random circuits and its application to routability measurement, in: Proceedings of the 1996 ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, February 1996, pp. 66\u201372.","DOI":"10.1145\/228370.228380"},{"key":"10.1016\/S0167-9260(99)00002-4_BIB2","unstructured":"Computer-Aided Design Benchmarking Laboratory, http:\/\/www.cbl.ncsu.edu\/benchmarks\/."},{"key":"10.1016\/S0167-9260(99)00002-4_BIB3","doi-asserted-by":"crossref","unstructured":"D. Ghosh, N. Kapur, J. Harlow III, F. Brglez, Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking, in: Proceedings of the Design, Automation end Test in Europe Conference, IEEE Computer Society, February 1998, pp. 656\u2013663.","DOI":"10.1109\/DATE.1998.655928"},{"key":"10.1016\/S0167-9260(99)00002-4_BIB4","doi-asserted-by":"crossref","unstructured":"M. Hutton, J. Rose, D. Corneil, Generation of synthetic sequential benchmark circuits, in: ACM\/SIGDA International Symposium on Field Programmable Gate Arrays, 1997, pp. 149\u2013155.","DOI":"10.1145\/258305.258333"},{"key":"10.1016\/S0167-9260(99)00002-4_BIB5","doi-asserted-by":"crossref","first-page":"1469","DOI":"10.1109\/T-C.1971.223159","article-title":"On a pin versus block relationship for partitions of logic graphs","volume":"C-20","author":"Landman","year":"1971","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0167-9260(99)00002-4_BIB6","doi-asserted-by":"crossref","unstructured":"E.S. Kuh, T. Ohtsuki, Recent advances in VLSI layout, Proceedings of the IEEE, Vol. 78, 1990, pp. 237\u2013263.","DOI":"10.1109\/5.52212"},{"key":"10.1016\/S0167-9260(99)00002-4_BIB7","doi-asserted-by":"crossref","unstructured":"D. Stroobandt, F.J. Kurdahi, On the characterization of multi-point nets in electronic designs, in: M.A. Bayoumi, G. Jullien (Eds.), Proceedings of the 8th Great Lakes Symposium on VLSI, IEEE Computer Society Press, February 1998, pp. 344\u2013350.","DOI":"10.1109\/GLSV.1998.665303"},{"key":"10.1016\/S0167-9260(99)00002-4_BIB8","unstructured":"D. Stroobandt, Generating new benchmark designs for evaluation of CAD tools and new computer architectures, Technical Report, University of Ghent, April 1998, ELIS Tech. Rep. DG 98-05."},{"key":"10.1016\/S0167-9260(99)00002-4_BIB9","doi-asserted-by":"crossref","first-page":"147","DOI":"10.1109\/TC.1972.5008919","article-title":"On the tradeoff between logic performance and circuit-to-pin ratio for LSI","volume":"C-21","author":"Russo","year":"1972","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S0167-9260(99)00002-4_BIB10","doi-asserted-by":"crossref","unstructured":"F. Brglez, D. Bryan, K. Kozminski, ISCAS\u201989 benchmarks, May 1989. Distributed on tape to participants of the Special Session on Sequential Test Generation, International Symposium on Circuits and Systems; partially characterized, in: F. Brglez, D. Bryan, K. Kozminski, Combinational Profiles of Sequential Benchmark Circuits, Proceedings of IEEE International Symposium on Circuits and Systems, pp. 1929\u20131934.","DOI":"10.1109\/ISCAS.1989.100747"},{"issue":"7","key":"10.1016\/S0167-9260(99)00002-4_BIB11","doi-asserted-by":"crossref","first-page":"911","DOI":"10.1109\/43.87601","article-title":"Ratio cut partitioning for hierarchical designs","volume":"10","author":"Wei","year":"1991","journal-title":"IEEE Trans. Comput.-Aided Des., Integrated Circuits Systems"},{"key":"10.1016\/S0167-9260(99)00002-4_BIB12","unstructured":"H. Van Marck, D. Stroobandt, J. Van Campenhout, Towards an extension of Rent's rule for describing local variations in interconnection complexity, in: S. Bai, J. Fan, X. Li, (Eds.), Proceedings of the fourth International Conference for Young Computer Scientists, Peking University Press, 1995, pp. 136\u2013141."},{"key":"10.1016\/S0167-9260(99)00002-4_BIB13","doi-asserted-by":"crossref","unstructured":"D. Stroobandt, J. Van Campenhout, Hierarchical test generation with built-in fault diagnosis, in: M.E. Kavanaugh (Ed.), Proceedings of the fifth Asian Test Symposium, IEEE Computer Society Press, November 1996, pp. 22\u201328.","DOI":"10.1109\/ATS.1996.555130"},{"key":"10.1016\/S0167-9260(99)00002-4_BIB14","unstructured":"F. Brglez, H. Fujiwara, A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran, June 1985, Distributed on tape to participants of the Special Session on ATPG and Fault Simulation, International Symposium on Circuits and Systems; partially characterized, in: F. Brglez, P. Pownall, R. Hum, Accelerated ATPG and Fault Grading via Testability Analysis, Proceedings of IEEE International Symposium on Circuits and Systems, pp. 695\u2013698."},{"key":"10.1016\/S0167-9260(99)00002-4_BIB15","unstructured":"C. Alpert, http:\/\/vlsicad.cs.ucla.edu\/\u00a0\u0303cheese\/benchmarks.html."}],"container-title":["Integration"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926099000024?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S0167926099000024?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T09:09:38Z","timestamp":1759136978000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S0167926099000024"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,7]]},"references-count":15,"journal-issue":{"issue":"2","published-print":{"date-parts":[[1999,7]]}},"alternative-id":["S0167926099000024"],"URL":"https:\/\/doi.org\/10.1016\/s0167-9260(99)00002-4","relation":{},"ISSN":["0167-9260"],"issn-type":[{"value":"0167-9260","type":"print"}],"subject":[],"published":{"date-parts":[[1999,7]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"Generating new benchmark designs using a multi-terminal net model","name":"articletitle","label":"Article Title"},{"value":"Integration","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/S0167-9260(99)00002-4","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1999 Elsevier Science B.V. All rights reserved.","name":"copyright","label":"Copyright"}]}}