{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,5,24]],"date-time":"2023-05-24T22:50:46Z","timestamp":1684968646761},"reference-count":25,"publisher":"Elsevier BV","issue":"14","license":[{"start":{"date-parts":[[2000,12,1]],"date-time":"2000-12-01T00:00:00Z","timestamp":975628800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2000,12]]},"DOI":"10.1016\/s1383-7621(00)00016-3","type":"journal-article","created":{"date-parts":[[2003,4,7]],"date-time":"2003-04-07T18:33:56Z","timestamp":1049740436000},"page":"1263-1274","source":"Crossref","is-referenced-by-count":4,"title":["Profiling in the ASP codesign environment"],"prefix":"10.1016","volume":"46","author":[{"given":"Sri","family":"Parameswaran","sequence":"first","affiliation":[]},{"given":"Matthew F.","family":"Parkinson","sequence":"additional","affiliation":[]},{"given":"Peter","family":"Bartlett","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(00)00016-3_BIB1","unstructured":"P. Ashenden, VHDL Cookbook, Internet"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB2","unstructured":"MEBS, Internet"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB3","series-title":"Performance Engineering of Software Systems","author":"Smith","year":"1990"},{"issue":"4","key":"10.1016\/S1383-7621(00)00016-3_BIB4","doi-asserted-by":"crossref","first-page":"308","DOI":"10.1145\/32232.32234","article-title":"Attributes of the performance of central processing units: a relative performance prediction model","volume":"30","author":"Ein-Dor","year":"1987","journal-title":"Commun. ACM"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB5","doi-asserted-by":"crossref","unstructured":"A.C. Shaw, Reasoning about time in higher-level language software, IEEE Trans. Software Eng. 15 (7) 1989","DOI":"10.1109\/32.29487"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB6","doi-asserted-by":"crossref","unstructured":"A. C. Shaw, Deterministic timing schema for parallel programs, in: Proceedings of the Fiveth International Parallel Processing Symposium, IEEE Computer Society Press, Silver Spring, MD, 1991, pp. 56\u201363","DOI":"10.1109\/IPPS.1991.153757"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB7","doi-asserted-by":"crossref","unstructured":"C.H. Park and A.C. Shaw, Experiments with a program timing tool based on source-level timing schema, IEEE Trans. Comput., May 1991, pp. 48\u201357","DOI":"10.1109\/2.76286"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB8","doi-asserted-by":"crossref","unstructured":"Th. Ball, J.R. Larus, Optimally profiling and tracing programs, in: ACM Sigplan Symposium Principles of Programming Language, Albuquerque 92, pp. 59\u201370","DOI":"10.1145\/143165.143180"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB9","doi-asserted-by":"crossref","unstructured":"W. Ye, R. Ernst, Th. Benner, J. Henkel, Fast timing analysis for hardware\u2013software co-synthesis, in: Proc. ICCD'93, IEEE Computer Society Press, Silver Spring, MD, 1993","DOI":"10.1109\/ICCD.1993.393335"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB10","unstructured":"M.F. Parkinson, P.M. Taylor, S. Parameswaran, An automated hardware\/software codesign (HSC) using VHDL, in: Proceedings of the First Asia Pacific Conference on Hardware Description Languages and their Applications (APCHDLSA '93), December 1993"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB11","unstructured":"M.F. Parkinson, P.M. Taylor, S. Parameswaran, A profiler for automated translation of signal processing algorithms into high speed hardware\/software hybrid architectures, in: Proceedings of Microelectronics '93, October 1993"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB12","doi-asserted-by":"crossref","unstructured":"M.F. Parkinson, P.M. Taylor, S. Parameswaran, C to VHDL converter in a codesign environment, in: Proceedings of VHDL International Users Forum, May 1994","DOI":"10.1109\/VIUF.1994.323960"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB13","doi-asserted-by":"crossref","unstructured":"P.M. Athanas, H.F. Silverman, Processor reconfiguration through instruction-set metamorphosis, Comput. IEEE, March 1993, pp. 11\u201318","DOI":"10.1109\/2.204677"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB14","doi-asserted-by":"crossref","first-page":"13","DOI":"10.2307\/2282952","article-title":"Probability inequalities for sums of bounded random variables","volume":"58","author":"Hoeffding","year":"1963","journal-title":"Am. Stat. Assoc. J."},{"key":"10.1016\/S1383-7621(00)00016-3_BIB15","unstructured":"GNU CC, Reference manual, Internet"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB16","unstructured":"YACC, Reference manual, Internet"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB17","unstructured":"B. Bose, M.E. Tuna, S.D. Johnson, System factorisation in codesign, in: Proceedings of the 1993 IEEE International Conference on Computer Design (ICCD '93), October 1993"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB18","unstructured":"R. Ernst, J. Henkel, Hardware\u2013software codesign of embedded controllers based on hardware extraction, in: Handout from First International Workshop on Hardware\u2013Software Codesign, Estes Park, Colorado, 1992"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB19","doi-asserted-by":"crossref","unstructured":"R. Gupta, C.C. Coelho, G. DeMicheli, Synthesis and simulation of digital systems containing interacting hardware and software components, in: Proc. DAC, IEEE Computer Society Press, Los Alamitos, California, 1992, pp. 225\u2013230","DOI":"10.1109\/DAC.1992.227832"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB20","doi-asserted-by":"crossref","unstructured":"D. C. Chen, J. M. Rabaey, A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths, in: JSSC, December 1992, pp. 1895\u20131904,","DOI":"10.1109\/4.173120"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB21","doi-asserted-by":"crossref","unstructured":"P. Windirsch, H.-J. Herpel, A. Laudenbach, M. Glesner, Application-specific microelectronics for mechatronic systems, in: EURODAC 92, Hamburg, September 1992, pp. 194\u2013199","DOI":"10.1109\/EURDAC.1992.246243"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB22","unstructured":"K. Buchenrieder, C. Veith, CODES. A practical concurrent design environment, in: IEEE Workshop on Hardware\u2013Software Codesign, Estes Park, Colorado, October 1992"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB23","doi-asserted-by":"crossref","unstructured":"R.K. Gupta, G.D. Micheli, System-level synthesis using re-programmable components, in: EDAC'92, Brussels, February 1992, pp. 2\u20137","DOI":"10.1109\/EDAC.1992.205881"},{"key":"10.1016\/S1383-7621(00)00016-3_BIB24","unstructured":"N. Woo, W. Wolf, A. Dunlop, Compilation of a single specification into hardware and software, in: IEEE Workshop on Hardware\u2013Software Codesign, Estes Park, Colorado, October 1992"},{"issue":"7","key":"10.1016\/S1383-7621(00)00016-3_BIB25","doi-asserted-by":"crossref","first-page":"965","DOI":"10.1109\/5.293155","article-title":"Hardware\u2013software codesign of embedded systems and prolog","volume":"82","author":"Wolf","year":"1994","journal-title":"Proc. IEEE"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762100000163?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762100000163?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2020,1,9]],"date-time":"2020-01-09T15:48:32Z","timestamp":1578584912000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762100000163"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,12]]},"references-count":25,"journal-issue":{"issue":"14","published-print":{"date-parts":[[2000,12]]}},"alternative-id":["S1383762100000163"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(00)00016-3","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2000,12]]}}}