{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T02:51:45Z","timestamp":1648781505725},"reference-count":34,"publisher":"Elsevier BV","issue":"13","license":[{"start":{"date-parts":[[2000,11,1]],"date-time":"2000-11-01T00:00:00Z","timestamp":973036800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2000,11]]},"DOI":"10.1016\/s1383-7621(00)00021-7","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T16:57:54Z","timestamp":1027616274000},"page":"1205-1230","source":"Crossref","is-referenced-by-count":3,"title":["Analytical modeling of multithreaded architectures"],"prefix":"10.1016","volume":"46","author":[{"given":"Vladimir","family":"Vlassov","sequence":"first","affiliation":[]},{"given":"Rassul","family":"Ayani","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(00)00021-7_BIB1","doi-asserted-by":"crossref","first-page":"525","DOI":"10.1109\/71.159037","article-title":"Performance tradeoffs in multithreaded processors","volume":"3","author":"Agarwal","year":"1992","journal-title":"IEEE Trans. Par. Dist. Systems"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB2","doi-asserted-by":"crossref","unstructured":"A. Agarwal, R. Bianchini, D. Chaiken, K.L. Johnson, D. Kranz, J. Kubiatowicz, B.-H. Lim, K. Mackenzie, D. Yeung, The MIT Alewife machine: architecture and performance, in: Proceedings of the ISCA'95, ACM, New York, 1995, pp. 2\u201313","DOI":"10.1145\/223982.223985"},{"issue":"3","key":"10.1016\/S1383-7621(00)00021-7_BIB3","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1109\/40.216748","article-title":"Sparcle: an evolutionary processor design for large-scale multiprocessors","volume":"13","author":"Agarwal","year":"1993","journal-title":"IEEE Micro"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB4","doi-asserted-by":"crossref","unstructured":"R. Alverson, D. Callahan, D. Cummings, B. Koblenz, A. Porterfield, B. Smith, The tera computer system, in: Proceedings of the International Conference on Supercomputing, ACM SIGARCH Computer Architecture News, vol. 18, 1990, pp. 1\u20136","DOI":"10.1145\/255129.255132"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB5","doi-asserted-by":"crossref","unstructured":"S.H. Bokhari, D.J. Mavriplis, The tera multithreaded architecture and unstructured meshes, ICASE Interim Report No. 33, NASA\/CR-1998-208953, 1998","DOI":"10.1006\/jcph.1998.6036"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB6","doi-asserted-by":"crossref","unstructured":"B. Boothe, A. Ranade, Improved multithreading techniques for hiding communication latency in multiprocessors, in: Proceedings of the ISCA'92, ACM, New York, 1992, pp. 223\u2013241","DOI":"10.1145\/139669.139729"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB7","doi-asserted-by":"crossref","first-page":"38","DOI":"10.1109\/6.402166","article-title":"Multithreaded processor architectures","volume":"32","author":"Byrd","year":"1995","journal-title":"IEEE Spectrum"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB8","doi-asserted-by":"crossref","unstructured":"R.S. Chappel, J. Stark, S.P. Kim, S.K. Reinhardt, Y.N. Patt, Simultaneous Subordinate Microthreading (SSMT), in: Proceedings of the ISCA'99, IEEE Computer Soc. Press, Silver Spring, MD, 1999, pp. 186\u2013195","DOI":"10.1145\/307338.300995"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB9","series-title":"Parallel Computer Architecture: A Hardware\/Software Approach","author":"Culler","year":"1998"},{"issue":"3","key":"10.1016\/S1383-7621(00)00021-7_BIB10","doi-asserted-by":"crossref","first-page":"225","DOI":"10.1145\/356733.356735","article-title":"The operational analysis of queueing network models","volume":"10","author":"Denning","year":"1978","journal-title":"Computing Surveys"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB11","series-title":"State-of-the-Art in Performance Modeling and Simulation of Advanced Computer Systems","article-title":"Performance modeling of a multithreaded processor spectrum","author":"Dubey","year":"1996"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB12","doi-asserted-by":"crossref","unstructured":"P.K. Dubey, A. Krishna, M.S. Squillante, Analytic performance modeling for a spectrum of multithreaded processor architectures, in: Proceedings of the MASCOTS'95, IEEE Computer Soc. Press, Silver Spring, MD, 1995, pp. 110\u2013122","DOI":"10.1109\/MASCOT.1995.378700"},{"issue":"5","key":"10.1016\/S1383-7621(00)00021-7_BIB13","doi-asserted-by":"crossref","first-page":"12","DOI":"10.1109\/40.621209","article-title":"Simultaneous multithreading: a platform for next-generation processors","volume":"15","author":"Eggers","year":"1997","journal-title":"IEEE Micro"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB14","doi-asserted-by":"crossref","unstructured":"M. Fillo, S.W. Keckler, W.J. Dally, N.P. Carter, A. Chang, Y. Gurevich, W.S. Lee, The M-machine multicomputer, in: Proceedings of the International Symposium on Microarchitecture, IEEE Computer Soc. Press, Silver Spring, MD, 1995, pp. 146\u2013157","DOI":"10.1109\/MICRO.1995.476820"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB15","unstructured":"W.K. Giloi, Towards the next generation parallel computers: MANNA and META, in: Proceedings of the Workshop on Parallel Programming and Computation (ZEUS '95), IOS Press, 1995, pp. 3\u201312"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB16","doi-asserted-by":"crossref","unstructured":"A. Gupta, J. Henessy, K. Gharachorloo, T. Mowry, W.-D. Weber, Comparative evaluation of latency reducing and tolerating techniques, in: Proceedings of the ISCA'91, IEEE Computer Soc. Press, Silver Spring, MD, 1991, pp. 254\u2013263","DOI":"10.1145\/115952.115978"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB17","series-title":"Computer Architecture: A Quantitative Approach","author":"Hennessy","year":"1996"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB18","unstructured":"Kai Hwang, Advanced Computer Architecture: Parallelism, Scalability, Programmability, McGraw-Hill, New York, 1993"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB19","doi-asserted-by":"crossref","unstructured":"R A. Iannucci, G.R. Gao, R.H. Halstead, Jr., B. Smith (Eds.), Multithreaded Computer Architecture. A Summary of the State of the Art, The Kluwer International Series in Engineering and Computer Science, vol. 281, Kluwer Academic Publishers, Boston, 1994","DOI":"10.1007\/978-1-4615-2698-8"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB20","series-title":"Queuing Systems","author":"Kleinrock","year":"1975"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB21","doi-asserted-by":"crossref","first-page":"176","DOI":"10.1109\/12.752659","article-title":"Effects of multithreading on cache performance","volume":"48","author":"Kwak","year":"1999","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S1383-7621(00)00021-7_BIB22","doi-asserted-by":"crossref","unstructured":"O.C. Maquelin, H.H.J. Hum, G.R. Gao, Costs and benefits of multithreading with off-the-shelf risc processors, in: Proceedings of the Euro-Par'95, Lecture Notes in Computer Science, vol. 966, Springer, Berlin, 1995, pp. 117\u2013128","DOI":"10.1007\/BFb0020459"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB23","doi-asserted-by":"crossref","unstructured":"S.W. Moore, Multithreaded Processor Design, The Kluwer International Series in Engineering and Computer Science, vol. 358, Kluwer Academic Publishers, Boston, 1996","DOI":"10.1007\/978-1-4613-1383-0"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB24","unstructured":"R.R. Muntz, J.W. Wong, Asymptotic properties of closed queueing network models, in: Proceedings of the Eighth Princeton Conference Information Sciences and Systems, Department of EECS, Princeton University Press, Princeton, NJ, 1974, pp. 348\u2013352"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB25","doi-asserted-by":"crossref","unstructured":"S.S. Nemawarkar, G.R. Gao, Measurement and modeling of EARTH-MANNA multithreaded architecture, in: Proceedings of the MASCOTS'96, IEEE Computer Soc. Press, Silver Spring, MD, 1996, pp. 109\u2013114","DOI":"10.1109\/MASCOT.1996.501002"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB26","doi-asserted-by":"crossref","unstructured":"S.S. Nemawarkar, R. Govindarajan, G.R. Gao, V.K. Agarwal, Analysis of multithreaded multiprocessors with distributed shared memory, in: Proceedings of the IEEE Symposium on Parallel and Distribution Processing, IEEE Computer Soc. Press, Silver Spring, MD, 1993, pp. 114\u2013121","DOI":"10.1109\/SPDP.1993.395543"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB27","doi-asserted-by":"crossref","unstructured":"S.S. Nemawarkar, R. Govindarajan, G.R. Gao, V.K. Agarwal, W.W. Koczkodaj, P.E. Lauer, A.A. Toptsis, Performance evaluation of latency tolerant architectures, in: Proceedings of the International Conference on Computing and Information (ICCI), IEEE Computer Soc. Press, Silver Spring, MD, 1992, pp. 183\u2013186","DOI":"10.1109\/ICCI.1992.227677"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB28","doi-asserted-by":"crossref","unstructured":"G.M. Papadopoulos, D.E. Culler, Monsoon: an explicit token-store architecture, in: Proceedings of the ISCA'90, IEEE Computer Soc. Press, Silver Spring, MD, 1990, pp. 82\u201391","DOI":"10.1145\/325164.325117"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB29","unstructured":"R.H. Saavedra-Barrera, D.E. Culler, An Analytical Solution for a Markov Chain Modeling Multithreaded Execution, Technical Report UCB\/CSD-91-623, University of California, Berkeley, 1991"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB30","doi-asserted-by":"crossref","unstructured":"R.H. Saavedra-Barrera, D.E. Culler, T. von Eicken, Analysis of multithreaded architectures for parallel computing, in: Proceedings of the ACM Symposium on Parallel Algorithms and Architectures, 1990, pp. 169\u2013178","DOI":"10.1145\/97444.97683"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB31","unstructured":"B.J. Smith, Architecture and applications of the HEP multiprocessor computer system, SPIE 298 (1981) 241\u2013248"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB32","doi-asserted-by":"crossref","unstructured":"D.M. Tullsen, S.J. Eggers, H.M. Levy, Simultaneous multithreading: maximizing on-chip parallelism, in: Proceedings of the ISCA'95, IEEE Computer Soc. Press, Silver Spring, MD, 1995, pp. 392\u2013403","DOI":"10.1145\/223982.224449"},{"issue":"4","key":"10.1016\/S1383-7621(00)00021-7_BIB33","doi-asserted-by":"crossref","first-page":"219","DOI":"10.1177\/003754979706800403","article-title":"Modeling and simulation of multithreaded architectures","volume":"68","author":"Vlassov","year":"1997","journal-title":"Simulation"},{"key":"10.1016\/S1383-7621(00)00021-7_BIB34","doi-asserted-by":"crossref","unstructured":"V. Vlassov, L.-E. Thorelli, Analytical models of multithreading with data prefetching, in: Proceedings of the Euro-Par'96, Lyon, France, August 1996, Lecture Notes in Computer Science, vol. 1124, Springer, Berlin, 1996, pp. 714\u2013723","DOI":"10.1007\/BFb0024768"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762100000217?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762100000217?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2020,1,17]],"date-time":"2020-01-17T02:34:54Z","timestamp":1579228494000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762100000217"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,11]]},"references-count":34,"journal-issue":{"issue":"13","published-print":{"date-parts":[[2000,11]]}},"alternative-id":["S1383762100000217"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(00)00021-7","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2000,11]]}}}