{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,22]],"date-time":"2025-03-22T08:27:36Z","timestamp":1742632056708,"version":"3.30.1"},"reference-count":32,"publisher":"Elsevier BV","issue":"14","license":[{"start":{"date-parts":[[2000,12,1]],"date-time":"2000-12-01T00:00:00Z","timestamp":975628800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2000,12]]},"DOI":"10.1016\/s1383-7621(00)00027-8","type":"journal-article","created":{"date-parts":[[2003,4,7]],"date-time":"2003-04-07T18:33:56Z","timestamp":1049740436000},"page":"1321-1334","source":"Crossref","is-referenced-by-count":11,"title":["ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs"],"prefix":"10.1016","volume":"46","author":[{"given":"Wolfgang","family":"G\u00fcnther","sequence":"first","affiliation":[]},{"given":"Rolf","family":"Drechsler","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(00)00027-8_BIB1","unstructured":"Actel. ACT TM1 series FPGAs. Also available at http:\/\/www.actel.com\/docs\/databook97\/section01\/97s01d07.pdf, 1997"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB2","unstructured":"Actel. Actel DeskTOP CD. See http:\/\/www.actel.com\/products\/systems\/desktop.html, 1999"},{"year":"1992","series-title":"Field-Programmable Gate Arrays","author":"Brown","key":"10.1016\/S1383-7621(00)00027-8_BIB3"},{"issue":"8","key":"10.1016\/S1383-7621(00)00027-8_BIB4","doi-asserted-by":"crossref","first-page":"677","DOI":"10.1109\/TC.1986.1676819","article-title":"Graph-based algorithms for Boolean function manipulation","volume":"35","author":"Bryant","year":"1986","journal-title":"IEEE Trans. Comp."},{"key":"10.1016\/S1383-7621(00)00027-8_BIB5","doi-asserted-by":"crossref","unstructured":"P. Buch, A. Narayan, A.R. Newton, A.L, Sangiovanni-Vincentelli, Logic synthesis for large pass transistor circuits, in: Proceedings of the International Conference on CAD, 1997, pp. 663\u2013670","DOI":"10.1109\/ICCAD.1997.643609"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB6","doi-asserted-by":"crossref","unstructured":"R. Chaudhry, T.-H. Liu, A. Aziz, J.L. Burns, Area-oriented synthesis for pass-transistor logic, in: Proceedings of the International Conference on Computer Design, 1998, pp. 160\u2013167","DOI":"10.1109\/ICCD.1998.727037"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB7","unstructured":"C.-H. Chen, C.-Y. Tsui, Timing optimization of logic network using gate duplication, in: Proceedings of the ASP Design Automation Conference, 1999, pp. 233\u2013234"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB8","doi-asserted-by":"crossref","unstructured":"K.C. Chen, S. Muroga, Timing optimization for multi-level combinational networks, in: Proceedings of the Design Automation Conference, 1990, pp. 339\u2013344","DOI":"10.1145\/123186.105253"},{"year":"1994","series-title":"Synthesis and Optimization of Digital Circuits","author":"De Micheli","key":"10.1016\/S1383-7621(00)00027-8_BIB9"},{"issue":"6","key":"10.1016\/S1383-7621(00)00027-8_BIB10","first-page":"364","article-title":"A genetic algorithm for variable ordering of OBDDs","volume":"143","author":"Drechsler","year":"1996","journal-title":"IEE Proceedings"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB11","doi-asserted-by":"crossref","unstructured":"R. Drechsler, N. Drechsler, W. G\u00fcnther, Fast exact minimization of BDDs, IEEE Trans. CAD 19 (3) (2000) 384\u2013389","DOI":"10.1109\/43.833206"},{"issue":"7","key":"10.1016\/S1383-7621(00)00027-8_BIB12","doi-asserted-by":"crossref","first-page":"909","DOI":"10.1109\/43.391740","article-title":"Combinational and sequential logic optimization by redundancy addition and removal","volume":"14","author":"Entrena","year":"1995","journal-title":"IEEE Trans. CAD"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB13","doi-asserted-by":"crossref","unstructured":"S. Ercolani, G.D. Micheli, Technology mapping for electrically programmable gate arrays, in: Proceedings of the Design Automation Conference, 1991, pp. 234\u2013239","DOI":"10.1145\/127601.127671"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB14","doi-asserted-by":"crossref","unstructured":"J. Espejo, L. Entrena, E. San Millan, E. Olias, Logic restructuring for MUX-based FPGAs, in: EUROMICRO, 1999, pp. 161\u2013168","DOI":"10.1109\/EURMIC.1999.794462"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB15","unstructured":"W. G\u00fcnther, R. Drechsler, BDD minimization by linear transformations, in: Proceedings of the Advanced Computer Systems, 1998, pp. 525\u2013532"},{"year":"1996","series-title":"Logic Synthesis and Verification Algorithms","author":"Hachtel","key":"10.1016\/S1383-7621(00)00027-8_BIB16"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB17","doi-asserted-by":"crossref","unstructured":"Y. Hong, P.A. Beerel, J.R. Burch, K.L. McMillan, Safe BDD minimization using don't cares, in: Proceedings of the Design Automation Conference, 1997, pp. 208\u2013213","DOI":"10.1109\/DAC.1997.597145"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB18","doi-asserted-by":"crossref","unstructured":"K. Karplus, Amap: a technology mapper for selector-based field-programmable gate arrays, in: Proceedings of the Design Automation Conference, 1991, pp. 244\u2013247","DOI":"10.1145\/127601.127673"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB19","unstructured":"K. Karplus, ITEM: an if-then-else minimizer for logic synthesis, Technical report, University of California, Santa Cruz, 1992"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB20","doi-asserted-by":"crossref","unstructured":"K. Keutzer, Dagon: Technology binding and local optimization by DAG matching, in: Proceedings of the Design Automation Conference, 1987, pp. 341\u2013347","DOI":"10.1145\/37888.37940"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB21","doi-asserted-by":"crossref","unstructured":"C. Meinel, F. Somenzi, T, Theobald. Linear sifting of decision diagrams, in: Proceedings of the Design Automation Conference, 1997, pp. 202\u2013207","DOI":"10.1109\/DAC.1997.597144"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB22","doi-asserted-by":"crossref","unstructured":"J. Mohnke, P. Molitor, S. Malik, Limits of using signatures for permutation independent Boolean comparison, in: Proceedings of the ASP Design Automation Conference, 1995, pp. 459\u2013464","DOI":"10.1145\/224818.224955"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB23","doi-asserted-by":"crossref","unstructured":"R. Murgai, R.K. Brayton, A.L. Sangiovanni-Vincentelli, An improved synthesis algorithm for multiplexor-based PGA's, in: Proceedings of the Design Automation Conference, 1992, pp. 380\u2013386","DOI":"10.1109\/DAC.1992.227774"},{"year":"1995","series-title":"Logic Synthesis for Field-Programmable Gate Arrays","author":"Murgai","key":"10.1016\/S1383-7621(00)00027-8_BIB24"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB25","doi-asserted-by":"crossref","unstructured":"R. Murgai, Y. Nishizaki, N. Shenoy, R.K. Brayton, A. Sangiovanni-Vincentelli, Logic synthesis for programmable gate arrays, in: Proceedings of the Design Automation Conference, 1990, pp. 620\u2013625","DOI":"10.1145\/123186.123421"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB26","unstructured":"S. Panda, F. Somenzi, Who are the variables in your neighborhood, in: Proceedings of the International Conference on CAD, 1995, pp. 74\u201377"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB27","doi-asserted-by":"crossref","unstructured":"S. Panda, F. Somenzi, B.F. Plessier, Symmetry detection and dynamic variable ordering of decision diagrams, in: Proceedings of the International Conference on CAD, 1994, pp. 628\u2013631","DOI":"10.1109\/ICCAD.1994.629887"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB28","doi-asserted-by":"crossref","unstructured":"B. Rohfleisch, B. Wurth, K. Antreich, Logic clause analysis for delay optimization, in: Proceedings of the Design Automation Conference, 1995, pp. 668\u2013672","DOI":"10.1145\/217474.217608"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB29","doi-asserted-by":"crossref","unstructured":"R. Rudell, Dynamic variable ordering for ordered binary decision diagrams, in: Proceedings of the International Conference on CAD, 1993, pp. 42\u201347","DOI":"10.1109\/ICCAD.1993.580029"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB30","doi-asserted-by":"crossref","unstructured":"C. Scholl, B. Becker, On the generation of multiplexer circuits for pass transistor logic, in: Proceedings of the Design, Automation and Test in Europe, 2000, pp. 372\u2013378","DOI":"10.1145\/343647.343800"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB31","unstructured":"E. Sentovich, K. Singh, L. Lavagno, Ch. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, A. Sangiovanni-Vincentelli, SIS: A system for sequential circuit synthesis, Technical report, University of Berkeley, 1992"},{"key":"10.1016\/S1383-7621(00)00027-8_BIB32","unstructured":"F. Somenzi, CUDD: CU Decision Diagram Package Release 2.3.0, University of Colorado at Boulder, 1998"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762100000278?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762100000278?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2024,12,4]],"date-time":"2024-12-04T03:50:35Z","timestamp":1733284235000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762100000278"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,12]]},"references-count":32,"journal-issue":{"issue":"14","published-print":{"date-parts":[[2000,12]]}},"alternative-id":["S1383762100000278"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(00)00027-8","relation":{},"ISSN":["1383-7621"],"issn-type":[{"type":"print","value":"1383-7621"}],"subject":[],"published":{"date-parts":[[2000,12]]}}}