{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,5]],"date-time":"2024-12-05T01:10:18Z","timestamp":1733361018698,"version":"3.30.1"},"reference-count":32,"publisher":"Elsevier BV","issue":"10","license":[{"start":{"date-parts":[[2002,4,1]],"date-time":"2002-04-01T00:00:00Z","timestamp":1017619200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2002,4]]},"DOI":"10.1016\/s1383-7621(01)00036-4","type":"journal-article","created":{"date-parts":[[2002,10,14]],"date-time":"2002-10-14T20:48:11Z","timestamp":1034628491000},"page":"847-867","source":"Crossref","is-referenced-by-count":39,"title":["A prototype of a VHDL-based fault injection tool: description and application"],"prefix":"10.1016","volume":"47","author":[{"given":"J.C","family":"Baraza","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J","family":"Gracia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D","family":"Gil","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.J","family":"Gil","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"year":"1992","series-title":"Dependability, Basic Concepts and Terminology","author":"Laprie","key":"10.1016\/S1383-7621(01)00036-4_BIB1"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB2","unstructured":"J. Arlat, Validation de la S\u00fbret\u00e9 de Fonctionnement par Injection de Fautes. M\u00e9thode-Mise en Oeuvre-Application, Th\u00e8se, Institut National Polytechnique de Toulouse, LAAS Reserche Report No. 90-399, Laboratoire d'Analyse et d'Architecture des Syst\u00e8mes du CNRS, Toulouse (France), December 1990"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB3","unstructured":"P.J. Gil, Sistema Tolerante a Fallos con Procesador de Guardia: Validaci\u00f3n mediante Inyecci\u00f3n F\u0131\u0301sica de Fallos, Tesis Doctoral, Departamento de Ingenier\u0131\u0301a de Sistemas, Computadores y Autom\u00e1tica (DISCA), Universidad Polit\u00e9cnica de Valencia (Spain), September 1992"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB4","doi-asserted-by":"crossref","unstructured":"M. Sueh, T. Tsai, R.K. lyer, Fault Injection Techniques and Tools, IEEE Computer, April 1997, pp. 75\u201382","DOI":"10.1109\/2.585157"},{"issue":"6","key":"10.1016\/S1383-7621(01)00036-4_BIB5","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1109\/2.386985","article-title":"Fault injection: a method for validating computer-system dependability","volume":"28","author":"Clark","year":"1995","journal-title":"IEEE Computer"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB6","unstructured":"E. Jenn, Sur la validation des syst\u00e8mes tol\u00e9rant les fautes: injection de fautes dans des mod\u00e8les de simulation VHDL, Th\u00e8se, LAAS Reserche Report No. 94-361, Laboratoire d'Analyse et d'Architecture des Syst\u00e8mes du CNRS, Toulouse (France), 1994"},{"year":"1996","series-title":"Fault-Tolerant Computer System Design, ISBN: 0-13-057887-8","author":"Pradhan","key":"10.1016\/S1383-7621(01)00036-4_BIB7"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB8","doi-asserted-by":"crossref","unstructured":"R.J. Mart\u0131\u0301nez, P.J. Gil, G. Mart\u0131\u0301n, C. P\u00e9rez, J.J. Serrano, Experimental validation of high-speed fault-tolerant systems using physical fault injection, in: Proceedings of the Dependable Computing for Critical Applications 7 (DCCA-7), vol. 12, San Jose (USA), January 1999, pp. 249\u2013265","DOI":"10.1109\/DCFTS.1999.814299"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB9","unstructured":"J.C. Campelo, Dise\u00f1o y validaci\u00f3n de nodos de proceso tolerantes a fallos de sistemas industriales distribuidos, Tesis Doctoral, Departamento de Inform\u00e1tica de Sistemas y Computadores (DISCA), Universidad Polit\u00e9cnica de Valencia (Spain), 1999"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB10","unstructured":"IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-1993"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB11","unstructured":"D. Gil, Validaci\u00f3n de Sistemas Tolerantes a Fallos mediante inyecci\u00f3n de fallos en modelos VHDL, Tesis Doctoral, Departamento de Inform\u00e1tica de Sistemas y Computadores (DISCA), Universidad Polit\u00e9cnica de Valencia (Spain), 1999"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB12","first-page":"511","article-title":"A measurement-based model for workload dependence of CPU errors","volume":"C35","author":"lyer","year":"1986","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB13","doi-asserted-by":"crossref","unstructured":"D. Gil, J. Gracia, J.C. Baraza, P.J. Gil, A study of the effects of transient fault injection into the VHDL model of a fault-tolerant microcomputer system, in: Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), Palma de Mallorca (Spain), July 2000, pp. 73\u201379","DOI":"10.1109\/OLT.2000.856615"},{"issue":"4","key":"10.1016\/S1383-7621(01)00036-4_BIB14","doi-asserted-by":"crossref","first-page":"24","DOI":"10.1109\/54.544533","article-title":"A fault injection technique for VHDL behavioral-level models","volume":"13","author":"DeLong","year":"1996","journal-title":"IEEE Design and Test of Computers"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB15","doi-asserted-by":"crossref","unstructured":"V. Sieh, O. Tsch\u00e4che, F. Balbach, VERIFY: evaluation of reliability using VHDL-models with embedded fault descriptions, in: Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS-27), Seattle, Washington (USA), June 1997, pp. 32\u201336","DOI":"10.1109\/FTCS.1997.614074"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB16","series-title":"Performance and Fault Modelling with VHDL","first-page":"240","article-title":"Test generation and fault simulation for behavioural models","author":"Armstrong","year":"1992"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB17","doi-asserted-by":"crossref","first-page":"135","DOI":"10.1007\/BF00133499","article-title":"On behavior fault modeling for digital design","volume":"2","author":"Ghosh","year":"1991","journal-title":"Journal of Electronic Testing: Theory and Applications"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB18","unstructured":"D. Gil, J.V. Busquets, J.C. Baraza, P. Gil, Using VHDL in the techniques of fault injection based on simulation, in: Proceedings XIII Design of Circuits and Integrated Systems Conference (DCIS-98), Madrid (Spain), November 1998, pp. 174\u2013180"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB19","doi-asserted-by":"crossref","unstructured":"E. Jenn, J. Arlat, M. Rimen, J. Ohlsson, J. Karlsson, Fault injection into VHDL models: the MEFISTO tool, in: Proceedings of the 24th International Symposium on Fault-Tolerant Computing (FTCS-24), Austin, Texas (USA), June 1994, pp. 66\u201375","DOI":"10.1109\/FTCS.1994.315656"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB20","unstructured":"P.J. Ashenden, The VHDL CookBook, Technical Report. University of Adelaide, South Australia, 1992"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB21","doi-asserted-by":"crossref","unstructured":"J. Bou\u00e9, P. P\u00e9tillon, Y. Crouzet, MEFISTO-L: A VHDL-based fault injection tool for the experimental assessment of fault tolerance, in: Proceedings of the 28th International Symposium on Fault-Tolerant Computing (FTCS-28), Munich (Germany), June 1998, pp. 168\u2013173","DOI":"10.1109\/FTCS.1998.689467"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB22","unstructured":"M. Rim\u00e9n, J. Ohlsson, S. Svensson, MEFISTO: Multilevel Error and Fault Injection Simulation Tool. User's Manual, Chalmers University of Technology, Gothenburg (Sweden), 1997"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB23","doi-asserted-by":"crossref","unstructured":"P. Folkesson, S. Svensson, J. Karlsson, A comparison of simulation based and scan-chain implemented fault injection, in: 28th International Symposium on Fault-Tolerant Computing (FTCS-28), 1998","DOI":"10.1109\/FTCS.1998.689479"},{"issue":"8","key":"10.1016\/S1383-7621(01)00036-4_BIB24","doi-asserted-by":"crossref","first-page":"913","DOI":"10.1109\/12.238482","article-title":"Fault injection and dependability evaluation of fault-tolerant systems","volume":"42","author":"Arlat","year":"1993","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB25","unstructured":"Model Technology, ModelSim EE\/PLUS Reference Manual, 1998"},{"year":"1997","series-title":"Failure Mechanisms in Semiconductor Devices","author":"Amerasekera","key":"10.1016\/S1383-7621(01)00036-4_BIB26"},{"year":"1989","series-title":"Chip-Level Modelling with VHDL","author":"Armstrong","key":"10.1016\/S1383-7621(01)00036-4_BIB27"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB28","doi-asserted-by":"crossref","unstructured":"D. Gil, J.C. Baraza, J.V. Busquets, P.J. Gil, Fault injection into VHDL models: analysis of the error syndrome of a microcomputer system, in: Proceedings of the 24th Euromicro Conference (EUROMICRO 98), vol. 1, V\u00e4ster\u00e5s (Sweden), August 1998, pp. 418\u2013424","DOI":"10.1109\/EURMIC.1998.711835"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB29","doi-asserted-by":"crossref","unstructured":"J. Ohlsson, M. Rim\u00e9n, U. Gunneflo, A study of the effect of transient fault injection into a 32-bit RISC with built-in watchdog, in: Proceedings of the 22nd International Symposium on Fault Tolerant Computing (FTCS-22), Boston, USA, 1992, pp. 316\u2013325","DOI":"10.1109\/FTCS.1992.243569"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB30","doi-asserted-by":"crossref","unstructured":"J.C. Baraza, J. Gracia, D. Gil, P.J. Gil, A prototype of a VHDL-based fault injection tool, in: Proceedings of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT2000), Yamanashi (Japan), October 2000, pp. 396\u2013404","DOI":"10.1109\/DFTVS.2000.887180"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB31","doi-asserted-by":"crossref","unstructured":"H. Cha, E.M. Rudnick, G.S. Choi, J.H. Patel, R.K. Iyer, A fast and accurate gate-level transient fault simulation environment, in: Proceedings of the 23rd International Symposium on Fault-Tolerant Computing (FTCS-23), Toulouse-(France), June 1993, pp. 310\u2013319","DOI":"10.1109\/FTCS.1993.627334"},{"key":"10.1016\/S1383-7621(01)00036-4_BIB32","unstructured":"J. Gracia, J.C. Baraza, D. Gil, P.J. Gil, A study of the experimental validation of fault-tolerant systems using different VHDL-based fault injection techniques, in: Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), Taormina (Italy), July 2001, p. 140"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762101000364?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762101000364?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2024,12,5]],"date-time":"2024-12-05T00:36:28Z","timestamp":1733358988000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762101000364"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,4]]},"references-count":32,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2002,4]]}},"alternative-id":["S1383762101000364"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(01)00036-4","relation":{},"ISSN":["1383-7621"],"issn-type":[{"type":"print","value":"1383-7621"}],"subject":[],"published":{"date-parts":[[2002,4]]}}}