{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,13]],"date-time":"2026-05-13T17:38:06Z","timestamp":1778693886475,"version":"3.51.4"},"reference-count":22,"publisher":"Elsevier BV","issue":"4-5","license":[{"start":{"date-parts":[[2002,12,1]],"date-time":"2002-12-01T00:00:00Z","timestamp":1038700800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2002,12]]},"DOI":"10.1016\/s1383-7621(02)00121-2","type":"journal-article","created":{"date-parts":[[2002,12,2]],"date-time":"2002-12-02T15:06:36Z","timestamp":1038841596000},"page":"125-135","source":"Crossref","is-referenced-by-count":4,"title":["On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation"],"prefix":"10.1016","volume":"48","author":[{"given":"Dimitris","family":"Bakalis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emmanouil","family":"Kalligeros","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dimitris","family":"Nikolos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Haridimos T.","family":"Vergos","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"George","family":"Alexiou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(02)00121-2_BIB1","series-title":"Digital Systems Testing and Testable Design","author":"Abramovici","year":"1990"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB2","series-title":"Proceedings of the 5th International On-Line Testing Workshop","first-page":"86","article-title":"On low power BIST for carry save array multipliers","author":"Bakalis","year":"1999"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB3","series-title":"Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems","first-page":"121","article-title":"Low power dissipation in BIST schemes for modified Booth multipliers","author":"Bakalis","year":"1999"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB4","unstructured":"D. Bakalis, E. Kalligeros, D. Nikolos, H.T. Vergos, G. Alexiou, Low power BIST for Wallace tree-based fast multipliers, Computer Technology Institute Technical Report (TR99\/09\/07), Patras, Greece, 1999"},{"issue":"12","key":"10.1016\/S1383-7621(02)00121-2_BIB5","doi-asserted-by":"crossref","first-page":"1325","DOI":"10.1109\/43.736572","article-title":"Techniques for minimizing power dissipation in scan and combinational circuits during test application","volume":"17","author":"Dabholkar","year":"1998","journal-title":"IEEE Transactions on CAD of Integrated Circuits and Systems"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB6","series-title":"Proceedings of the VLSI Test Symposium","first-page":"407","article-title":"A test vector inhibiting technique for low energy BIST design","author":"Girard","year":"1999"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB7","series-title":"Proceedings of the 1st International Symposium on Quality Electronic Design","first-page":"173","article-title":"Low power testing of VLSI circuits: problems and solutions","author":"Girard","year":"2000"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB8","series-title":"Proceedings of the International Test Conference","first-page":"652","article-title":"Low power BIST design by hypergraph partitioning: methodology and architectures","author":"Girard","year":"2000"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB9","series-title":"Proceedings of the 8th Annual Symposium on Switching and Automata Theory","first-page":"161","article-title":"Testing for faults in cellular logic arrays","author":"Kautz","year":"1967"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB10","series-title":"Proceedings of the Southwest Symposium on Mixed-Signal Design","first-page":"87","article-title":"On-chip deterministic counter-based TPG with low heat dissipation","author":"Kavousianos","year":"1999"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB11","series-title":"Digital Design","author":"Morris Mano","year":"1991"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB12","series-title":"Proceedings of the Multi-Chip Module Conference","first-page":"24","article-title":"Bare die test","author":"Parkar","year":"1992"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB13","series-title":"Proceedings of the Design, Automation and Test in Europe Conference","first-page":"117","article-title":"An effective BIST architecture for fast multiplier cores","author":"Paschalis","year":"1999"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB14","series-title":"Arithmetic Built-In Self-Test for Embedded Systems","author":"Rajski","year":"1998"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB15","unstructured":"R. Roy, Scaling Towards Nanometer Technologies: Design for Test Challenges, Panel, Design Automation and Test in Europe Conference, 1999"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB16","series-title":"Proceedings of the International Conference on CAD","first-page":"402","article-title":"On average power dissipation and random pattern testability of CMOS combinational logic networks","author":"Shen","year":"1992"},{"issue":"9","key":"10.1016\/S1383-7621(02)00121-2_BIB17","doi-asserted-by":"crossref","first-page":"721","DOI":"10.1016\/S1383-7621(99)00041-7","article-title":"Testing and built-in self-test\u2013\u2013A survey","volume":"46","author":"Steininger","year":"2000","journal-title":"Journal of Systems Architecture"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB18","series-title":"Proceedings of the International Test Conference","first-page":"848","article-title":"DS-LFSR: a new BIST TPG for low heat dissipation","author":"Wang","year":"1997"},{"issue":"2","key":"10.1016\/S1383-7621(02)00121-2_BIB19","doi-asserted-by":"crossref","first-page":"256","DOI":"10.1109\/12.663775","article-title":"ATPG for heat dissipation minimization during test application","volume":"47","author":"Wang","year":"1998","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB20","series-title":"Principles of CMOS VLSI Design: A Systems Perspective","author":"Weste","year":"1992"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB21","series-title":"Proceedings of the 5th International On-Line Testing Workshop","first-page":"82","article-title":"Design and synthesis of programmable low power weighted random pattern generator","author":"Zhang","year":"1999"},{"key":"10.1016\/S1383-7621(02)00121-2_BIB22","series-title":"Proceedings of the VLSI Test Symposium","first-page":"4","article-title":"A distributed BIST control scheme for complex VLSI devices","author":"Zorian","year":"1993"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762102001212?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762102001212?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,4,2]],"date-time":"2019-04-02T08:56:01Z","timestamp":1554195361000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762102001212"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,12]]},"references-count":22,"journal-issue":{"issue":"4-5","published-print":{"date-parts":[[2002,12]]}},"alternative-id":["S1383762102001212"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(02)00121-2","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2002,12]]}}}