{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T17:36:53Z","timestamp":1649007413046},"reference-count":13,"publisher":"Elsevier BV","issue":"4-5","license":[{"start":{"date-parts":[[2002,12,1]],"date-time":"2002-12-01T00:00:00Z","timestamp":1038700800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2002,12]]},"DOI":"10.1016\/s1383-7621(02)00123-6","type":"journal-article","created":{"date-parts":[[2002,12,2]],"date-time":"2002-12-02T20:06:36Z","timestamp":1038859596000},"page":"151-173","source":"Crossref","is-referenced-by-count":0,"title":["Scheduling expression trees for delayed-load architectures"],"prefix":"10.1016","volume":"48","author":[{"given":"R.","family":"Venugopal","sequence":"first","affiliation":[]},{"given":"Y.N.","family":"Srikant","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(02)00123-6_BIB1","doi-asserted-by":"crossref","first-page":"488","DOI":"10.1145\/321958.321970","article-title":"Optimal code generation for expression trees","volume":"23","author":"Aho","year":"1976","journal-title":"J. ACM"},{"key":"10.1016\/S1383-7621(02)00123-6_BIB2","doi-asserted-by":"crossref","unstructured":"P. van Beck, K. Wilken, Fast optimal instruction scheduling for single-issue processors with arbitrary latencies, in: Proc. International Conference on Principles and Practice of Constraint Programming, Lecture Notes in Computer Science, vol. 2239, Springer-Verlag, 2001","DOI":"10.1007\/3-540-45578-7_52"},{"key":"10.1016\/S1383-7621(02)00123-6_BIB3","unstructured":"M. Heffernan, J. Liu, K. Wilken, Optimal instruction scheduling using integer linear programming, in: Proc. ACM PLDI Conference, 2000"},{"key":"10.1016\/S1383-7621(02)00123-6_BIB4","doi-asserted-by":"crossref","unstructured":"D. Kaestner, S. Winkel, ILP-based instruction scheduling for IA-64, LCTES\u201901, ACM PLDI Conference Workshop on Languages, Compilers, and Tools for Embedded Systems, 2001","DOI":"10.1145\/384197.384217"},{"issue":"5","key":"10.1016\/S1383-7621(02)00123-6_BIB5","doi-asserted-by":"crossref","first-page":"740","DOI":"10.1145\/213978.213987","article-title":"Efficient instruction scheduling for delayed-load archiectures","volume":"17","author":"Kurlander","year":"1995","journal-title":"ACM Trans. Prog. Lang. Syst."},{"key":"10.1016\/S1383-7621(02)00123-6_BIB6","doi-asserted-by":"crossref","unstructured":"R. Leupers, Instruction scheduling for clustered VLIW DSPs, Proc. IEEE Conf. Parallel Computing Technologies, 2000","DOI":"10.1109\/PACT.2000.888353"},{"key":"10.1016\/S1383-7621(02)00123-6_BIB7","doi-asserted-by":"crossref","unstructured":"T.A. Proebsting, C.N. Fischer, Linear-time, optimal code scheduling for delayed-load architectures, in: Proceedings of the ACM SIGPLAN \u201991 Conf. on Programming Language Design and Implementation, 1991, pp. 256\u2013267","DOI":"10.1145\/113445.113467"},{"key":"10.1016\/S1383-7621(02)00123-6_BIB8","doi-asserted-by":"crossref","unstructured":"J. Sanchez, A. Gonzalez, Instruction scheduling for clustered VLIW architectures, in: Proc. Int.Symp. Systems Synthesis, 2000","DOI":"10.1109\/ISSS.2000.874027"},{"issue":"6","key":"10.1016\/S1383-7621(02)00123-6_BIB9","doi-asserted-by":"crossref","first-page":"715","DOI":"10.1145\/321607.321620","article-title":"The generation of optimal code for arithmetic expressions","volume":"17","author":"Sethi","year":"1970","journal-title":"J. ACM"},{"key":"10.1016\/S1383-7621(02)00123-6_BIB10","doi-asserted-by":"crossref","first-page":"577","DOI":"10.1016\/0165-6074(94)90102-3","article-title":"Scheduling expression trees with register variables on delayed-load architectures","volume":"40","author":"Venugopal","year":"1994","journal-title":"Microproc. Microprog."},{"issue":"1","key":"10.1016\/S1383-7621(02)00123-6_BIB11","doi-asserted-by":"crossref","first-page":"49","DOI":"10.1016\/0096-0551(95)00001-K","article-title":"Scheduling expression trees with reusable registers on delayed-load architectures","volume":"21","author":"Venugopal","year":"1995","journal-title":"Comput. Lang."},{"key":"10.1016\/S1383-7621(02)00123-6_BIB12","unstructured":"R. Venugopal, Incremental Techniques for Code Generation Problems, Ph.D. thesis, Department of Computer Science and Automation, Indian Institute of Science, Bangalore, India, 1997"},{"key":"10.1016\/S1383-7621(02)00123-6_BIB13","doi-asserted-by":"crossref","unstructured":"H. Wu, J. Jaffer, R.H.C. Yap, Scheduling with timing constraints on a single RISC processor with 0\/1 latencies, in: Proc. International Conference on Principles and Practice of Constraint Programming, 2000","DOI":"10.1007\/3-540-45349-0_33"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762102001236?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762102001236?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2020,3,11]],"date-time":"2020-03-11T13:10:42Z","timestamp":1583932242000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762102001236"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,12]]},"references-count":13,"journal-issue":{"issue":"4-5","published-print":{"date-parts":[[2002,12]]}},"alternative-id":["S1383762102001236"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(02)00123-6","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2002,12]]}}}