{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,12]],"date-time":"2024-12-12T05:54:10Z","timestamp":1733982850832,"version":"3.30.2"},"reference-count":19,"publisher":"Elsevier BV","issue":"8-10","license":[{"start":{"date-parts":[[2003,3,1]],"date-time":"2003-03-01T00:00:00Z","timestamp":1046476800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2003,3]]},"DOI":"10.1016\/s1383-7621(03)00012-2","type":"journal-article","created":{"date-parts":[[2003,3,4]],"date-time":"2003-03-04T16:29:22Z","timestamp":1046795362000},"page":"285-310","source":"Crossref","is-referenced-by-count":2,"title":["New design methodology with efficient prediction of quality metrics for logic level design towards dynamic reconfigurable logic"],"prefix":"10.1016","volume":"48","author":[{"given":"Mahmoud","family":"Meribout","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masato","family":"Motomura","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(03)00012-2_BIB1","unstructured":"N. Dutt, C. Ramachandran, Benchmarks for the 1992 high level synthesis workshop, Tech. Rep, #92\u2013107, Dept. Inform. Comput. Sci., Univ. California, Irvine, 1992"},{"issue":"August","key":"10.1016\/S1383-7621(03)00012-2_BIB2","doi-asserted-by":"crossref","first-page":"955","DOI":"10.1109\/43.149767","article-title":"Predicting system-level area and delay for pipelined and non-pipelined designs","volume":"11","author":"Jain","year":"1992","journal-title":"IEEE Trans. Comput. Aided Des."},{"key":"10.1016\/S1383-7621(03)00012-2_BIB3","unstructured":"M. Meribout, M. Motomura, Method for compiling high level programs into hardware, Japanese Patent: JSP2000-313818, 2000"},{"key":"10.1016\/S1383-7621(03)00012-2_BIB4","doi-asserted-by":"crossref","unstructured":"M. Motomura et al., An embedded DRAM-FPGA chip with instantaneous logic reconfiguration, in: Symposium on VLSI Circuits, July 1997, pp. 55\u201356","DOI":"10.1109\/VLSIC.1997.623804"},{"year":"1994","series-title":"Task scheduling in parallel and distributed systems","author":"El-Rewini","key":"10.1016\/S1383-7621(03)00012-2_BIB5"},{"key":"10.1016\/S1383-7621(03)00012-2_BIB6","doi-asserted-by":"crossref","unstructured":"D. Chang, M. Marek-Sadowska, Buffer minimization and time-multiplexed I\/O on dynamically reconfigurable FPGA, in: Proc. ACM Int\u2019l Symp. FPGAs, 1997, pp. 142\u2013148","DOI":"10.1145\/258305.258331"},{"key":"10.1016\/S1383-7621(03)00012-2_BIB7","doi-asserted-by":"crossref","unstructured":"A. Dehon, DFPGA utilization and application, in: Proc. ACM Int\u2019l Symp. FPGAs, 1996, pp. 115\u2013121","DOI":"10.1109\/FPGA.1996.242438"},{"issue":"6","key":"10.1016\/S1383-7621(03)00012-2_BIB8","doi-asserted-by":"crossref","first-page":"565","DOI":"10.1109\/12.773794","article-title":"Partitioning sequential circuits on dynamically reconfigurable FPGAs","volume":"48","author":"Chang","year":"1999","journal-title":"IEEE Trans. Comput."},{"issue":"5","key":"10.1016\/S1383-7621(03)00012-2_BIB9","article-title":"A Unified lower bound estimation technique for high level synthesis","volume":"16","author":"Yong Ohm","year":"1997","journal-title":"IEEE Trans. Comput. Aided Des."},{"key":"10.1016\/S1383-7621(03)00012-2_BIB10","doi-asserted-by":"crossref","unstructured":"I. Robertson, J. Irvine, P. Lysaght, D. Robinson, Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series, in: Tenth ACM International Symposium on Field-Programmable Gate Arrays, Monterey, California, USA, February 2002","DOI":"10.1145\/503048.503068"},{"issue":"Janurary\u2013March","key":"10.1016\/S1383-7621(03)00012-2_BIB11","doi-asserted-by":"crossref","first-page":"53","DOI":"10.1109\/54.825677","article-title":"Adaptive multi-user On-line reconfigurable engine","volume":"17","author":"Rakhmatov","year":"2000","journal-title":"IEEE Des. Test Comput."},{"key":"10.1016\/S1383-7621(03)00012-2_BIB12","doi-asserted-by":"crossref","unstructured":"M.J. Worthlin, B.L. Hutchings, C. Worth, Synthesizing RTL hardware from java byte codes, in: Field Programmable Logic and Applications, Belfast, Northern Ireland, August 2001, pp. 123\u2013132","DOI":"10.1007\/3-540-44687-7_13"},{"key":"10.1016\/S1383-7621(03)00012-2_BIB13","unstructured":"Xilinx Inc., Virtex Series Configuration Architecture User Guides, version 1.5, September, 27th, 2000"},{"issue":"1","key":"10.1016\/S1383-7621(03)00012-2_BIB14","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/92.486081","article-title":"Programmable active memories: reconfigurable systems come of age","volume":"4","author":"Vuillemin","year":"1996","journal-title":"IEEE Trans. VLSI Syst."},{"key":"10.1016\/S1383-7621(03)00012-2_BIB15","doi-asserted-by":"crossref","unstructured":"C. Iseli, E. Sanchez, A C++ compiler for FPGA custom execution units synthesis, in: D.A. Buell, K.L. Pocek (Eds.), Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, April 1995, pp. 173\u2013179","DOI":"10.1109\/FPGA.1995.477423"},{"year":"1994","series-title":"Synthesis and Optimization of Digital Circuits","author":"De Micheli","key":"10.1016\/S1383-7621(03)00012-2_BIB16"},{"key":"10.1016\/S1383-7621(03)00012-2_BIB17","doi-asserted-by":"crossref","unstructured":"Y. Li, T. Callahan, E. Darnell, R. Harr, U. Kurke, J. Stockwood, Hardware-software co-design of embedded reconfigurable architectures, in Proc. Design Automation Conference, 2000","DOI":"10.1145\/337292.337559"},{"key":"10.1016\/S1383-7621(03)00012-2_BIB18","doi-asserted-by":"crossref","unstructured":"J.R. Hauser, J. Wawrzyneck, Garp: A MIPS processor with a reconfigurable coprocessor, in: Proc. IEEE Symposium on Field Custom Computing Machines, 1998, pp. 12\u201321","DOI":"10.1109\/FPGA.1997.624600"},{"key":"10.1016\/S1383-7621(03)00012-2_BIB19","unstructured":"R. Harr, The NIMPLE compiler for agile hardware: A research platform, in: Proc. 13th International Symposium on system Synthesis, 2000"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762103000122?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762103000122?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2024,12,11]],"date-time":"2024-12-11T22:20:21Z","timestamp":1733955621000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762103000122"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,3]]},"references-count":19,"journal-issue":{"issue":"8-10","published-print":{"date-parts":[[2003,3]]}},"alternative-id":["S1383762103000122"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(03)00012-2","relation":{},"ISSN":["1383-7621"],"issn-type":[{"type":"print","value":"1383-7621"}],"subject":[],"published":{"date-parts":[[2003,3]]}}}