{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T08:34:14Z","timestamp":1648802054141},"reference-count":18,"publisher":"Elsevier BV","issue":"13-15","license":[{"start":{"date-parts":[[2003,5,1]],"date-time":"2003-05-01T00:00:00Z","timestamp":1051747200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2003,5]]},"DOI":"10.1016\/s1383-7621(03)00024-9","type":"journal-article","created":{"date-parts":[[2003,5,13]],"date-time":"2003-05-13T01:09:24Z","timestamp":1052788164000},"page":"377-385","source":"Crossref","is-referenced-by-count":0,"title":["Modeling and evaluating the time overhead induced by BER in COMA multiprocessors"],"prefix":"10.1016","volume":"48","author":[{"given":"Mohsen","family":"Sharifi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Behrouz","family":"Zolfaghari","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(03)00024-9_BIB1","doi-asserted-by":"crossref","unstructured":"A. Agrawal et al., The MIT Alewife Machine: A Large Scale Distributed Shared Memory Multiprocessor, Research Report MIT\/LCS\/TM-454, MIT Laboratory for Computer Science, June 1991","DOI":"10.1007\/978-1-4615-3604-8_13"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB2","unstructured":"T. Anderson, Operating System Support for High Performance Multiprocessing, Ph.D. Thesis, University of Washington, Technical Report 91-08-10, August 1991"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB3","doi-asserted-by":"crossref","unstructured":"John B. Carter, Dilip Khandekar, Linus Camb, Distributed shared memory: where we are and where we should be headed, in: Proceedings of the Fifth Workshop on Hot Topics in Operating Systems, 1995","DOI":"10.1109\/HOTOS.1995.513466"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB4","doi-asserted-by":"crossref","unstructured":"F. Dahlgren, J. Torellas, Cache only memory architectures, IEEE Computer Magazine, June, 1999","DOI":"10.1109\/2.769448"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB5","unstructured":"S. Frank, H. Burkhardt, J. Rothinie, The KSR1: bridging the gap between shared memory and MMPs, in: Proceedings of Spring COMPCON\u201999, February 1993"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB6","doi-asserted-by":"crossref","unstructured":"A. Gefflaut et al., Tolerating node failures in cache only memory architectures, in: Proceedings of Supercomputing\u201994 Conference, November 1994","DOI":"10.1109\/SUPERC.1994.344300"},{"issue":"9","key":"10.1016\/S1383-7621(03)00024-9_BIB7","doi-asserted-by":"crossref","first-page":"44","DOI":"10.1109\/2.156381","article-title":"DDM\u2013\u2013A cache only memory architecture","volume":"25","author":"Hagersten","year":"1992","journal-title":"IEEE Computer"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB8","doi-asserted-by":"crossref","unstructured":"G.C. Hunt, M.L. Scott, Using Peer Support to Reduce Fault-Tolerant Overhead in Distributed Shared Memories, URCS Technical Report 626, June 1996","DOI":"10.21236\/ADA329899"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB9","doi-asserted-by":"crossref","unstructured":"A.M. Kermarrec, G. Cabillic, C. Morin, I. Puaut, A recoverable distributed shared memory integrating coherence and recoverability, in: Proceedings of the 25th International Symposium on Fault-Tolerant Computing, Los Alamitos, CA, INRIA, June 1995, pp. 289\u2013298","DOI":"10.1109\/FTCS.1995.466970"},{"issue":"3","key":"10.1016\/S1383-7621(03)00024-9_BIB10","doi-asserted-by":"crossref","first-page":"63","DOI":"10.1109\/2.121510","article-title":"The stanford DASH multiprocessor","volume":"25","author":"Lenosky","year":"1992","journal-title":"IEEE Computer"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB11","doi-asserted-by":"crossref","unstructured":"Christine Morin et al., COMA: an opportunity for building fault-tolerant scalable shared memory multiprocessors, in: Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, May 1996","DOI":"10.1145\/232973.232981"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB12","doi-asserted-by":"crossref","unstructured":"N. Neves, M. Castro, P. Guedes, A checkpoint protocol for an entry consistent shared memory system, in: Proceedings of the 13th ACM Symposium on Principles of Distributed Computing, Los Angeles, CA, August 1994","DOI":"10.1145\/197917.197973"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB13","unstructured":"J.P. Singh et al., SPLASH: Stanford Parallel Applications for Shared Memory, Technical Report CSL-TR-91-469, Computer System Laboratory, Stanford University, April 1991"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB14","doi-asserted-by":"crossref","unstructured":"Florin Sultan, Thu, D. Nguyen, Liviu Iftode, Scalable fault-tolerant distributed shared memory, in: Proceedings of Supercomputing Conference, Dallas, November 2000","DOI":"10.1109\/SC.2000.10014"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB15","doi-asserted-by":"crossref","unstructured":"Florin Sultan, Thu, D. Nguyen, Liviu Iftode, Limited-Size Logging for Fault-Tolerant Distributed Shared Memory with Independent Checkpointing, Rutgers University Technical Report DCS-TR-409, February 2000","DOI":"10.1109\/SC.2000.10014"},{"issue":"4","key":"10.1016\/S1383-7621(03)00024-9_BIB16","first-page":"91","article-title":"Modeling and evaluating the impact of relaxed inclusion in COMA multiprocessors","volume":"13","author":"Sharifi","year":"2002","journal-title":"IUST International Journal of Science and Technology"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB17","doi-asserted-by":"crossref","unstructured":"G. Suri, B. Janssen, W.K. Fuchs, Reduced overhead logging for rollback recovery in distributed shared memory, in: Proceedings of the 25th International Symposium on Fault-Tolerant Computing, June 1995","DOI":"10.1109\/FTCS.1995.466971"},{"key":"10.1016\/S1383-7621(03)00024-9_BIB18","unstructured":"J. Torellas, D. Padua, The Illinois aggressive COMA multiprocessor project (I_A COMA), in: Proceedings of the Frontiers of Massively Parallel Computing, October 1996"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762103000249?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762103000249?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2020,3,19]],"date-time":"2020-03-19T13:20:27Z","timestamp":1584624027000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762103000249"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,5]]},"references-count":18,"journal-issue":{"issue":"13-15","published-print":{"date-parts":[[2003,5]]}},"alternative-id":["S1383762103000249"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(03)00024-9","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2003,5]]}}}