{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T00:21:24Z","timestamp":1763684484719},"reference-count":18,"publisher":"Elsevier BV","issue":"1-2","license":[{"start":{"date-parts":[[2003,7,1]],"date-time":"2003-07-01T00:00:00Z","timestamp":1057017600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2003,7]]},"DOI":"10.1016\/s1383-7621(03)00062-6","type":"journal-article","created":{"date-parts":[[2003,7,16]],"date-time":"2003-07-16T16:18:16Z","timestamp":1058372296000},"page":"53-58","source":"Crossref","is-referenced-by-count":20,"title":["Residue number system to binary converter for the moduli set (2n\u22121,2n\u22121,2n+1)"],"prefix":"10.1016","volume":"49","author":[{"given":"Ahmad","family":"Hiasat","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andraos","family":"Sweidan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(03)00062-6_BIB1","series-title":"Residue Number System Arithmetic, Modern Applications in Digital Signal Processing","year":"1986"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB2","series-title":"Residue Arithmetic and its Applications to Computer Technology","author":"Szabo","year":"1967"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB3","doi-asserted-by":"crossref","unstructured":"G.C. Cardarilli, A. Nannarelli, M. Re, Reducing power dissipation in FIR filters using the residue number system, in: Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, Lansing, USA, August, 2000, pp. 214\u2013217","DOI":"10.1109\/MWSCAS.2000.951651"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB4","doi-asserted-by":"crossref","first-page":"1002","DOI":"10.1109\/82.782041","article-title":"Delta\u2013sigma modulator with large OSR using one-hot residue number system","volume":"46","author":"Chren","year":"1999","journal-title":"IEEE Trans. Circuits and Systems\u2013\u2013Part II"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB5","doi-asserted-by":"crossref","first-page":"2292","DOI":"10.1109\/49.895034","article-title":"Adaptive redundant residue number system coded multicarrier modulation","volume":"18","author":"Keller","year":"2000","journal-title":"IEEE J. Selected Areas Comm."},{"key":"10.1016\/S1383-7621(03)00062-6_BIB6","doi-asserted-by":"crossref","first-page":"298","DOI":"10.1109\/TCS.1985.1085689","article-title":"Fast memoryless, over 64 bits, residue to decimal converter","volume":"32","author":"Bernardson","year":"1985","journal-title":"IEEE Trans. Circuits and Systems"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB7","doi-asserted-by":"crossref","first-page":"1156","DOI":"10.1109\/31.7576","article-title":"An efficient residue to binary converter design","volume":"35","author":"Ibrahim","year":"1988","journal-title":"IEEE Trans. Circuits and Systems"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB8","doi-asserted-by":"crossref","first-page":"1441","DOI":"10.1109\/31.14470","article-title":"New efficient memoryless, residue to binary converter","volume":"35","author":"Sweidan","year":"1988","journal-title":"IEEE Trans. Circuits and Systems"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB9","doi-asserted-by":"crossref","first-page":"661","DOI":"10.1109\/82.471401","article-title":"A high-speed realization of a residue number system converter","volume":"42","author":"Piestrak","year":"1995","journal-title":"IEEE Trans. Circuits and Systems\u2013\u2013Part II"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB10","doi-asserted-by":"crossref","first-page":"53","DOI":"10.1109\/82.559370","article-title":"The digital parallel method for fast RNS to weighted number system conversion for specific moduli (2k\u22121,2k,2k+1)","volume":"44","author":"Gallaher","year":"1997","journal-title":"IEEE Trans. Circuits and Systems\u2013\u2013Part II"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB11","doi-asserted-by":"crossref","first-page":"852","DOI":"10.1109\/12.795127","article-title":"Fast converter for 3 moduli RNS using new property of CRT","volume":"48","author":"Conway","year":"1999","journal-title":"IEEE Trans. Computers"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB12","doi-asserted-by":"crossref","first-page":"1437","DOI":"10.1109\/81.883343","article-title":"An improved residue to binary converter","volume":"47","author":"Wang","year":"2000","journal-title":"IEEE Trans. Circuits and Systems\u2013\u2013Part I"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB13","doi-asserted-by":"crossref","first-page":"204","DOI":"10.1109\/82.661651","article-title":"Residue to binary arithmetic converter for the moduli (2k,2k\u22121,2k\u22121\u22121)","volume":"45","author":"Hiasat","year":"1998","journal-title":"IEEE Trans. Circuits and Systems\u2013\u2013Part II"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB14","doi-asserted-by":"crossref","first-page":"1576","DOI":"10.1109\/82.899659","article-title":"A high-speed residue-to-binary converter for the three-moduli (2k,2k\u22121,2k\u22121\u22121)","volume":"47","author":"Wang","year":"2000","journal-title":"IEEE Trans. Circuits and Systems\u2013\u2013Part II"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB15","series-title":"Computer Arithmetic: Principles, Architecture and Design","author":"Hwang","year":"1979"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB16","series-title":"Introduction to Arithmetic for Digital Systems Designers","author":"Waser","year":"1982"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB17","doi-asserted-by":"crossref","first-page":"673","DOI":"10.1109\/12.863036","article-title":"High-speed parallel-prefix modulo 2n\u22121 adders","volume":"49","author":"Kalampoukas","year":"2000","journal-title":"IEEE Trans. Computers"},{"key":"10.1016\/S1383-7621(03)00062-6_BIB18","doi-asserted-by":"crossref","first-page":"84","DOI":"10.1109\/12.980018","article-title":"High-speed and reduced-area modular adder structures for RNS","volume":"51","author":"Hiasat","year":"2002","journal-title":"IEEE Trans. Computers"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762103000626?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762103000626?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,3,17]],"date-time":"2019-03-17T12:50:53Z","timestamp":1552827053000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762103000626"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,7]]},"references-count":18,"journal-issue":{"issue":"1-2","published-print":{"date-parts":[[2003,7]]}},"alternative-id":["S1383762103000626"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(03)00062-6","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2003,7]]}}}