{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,14]],"date-time":"2024-12-14T05:15:44Z","timestamp":1734153344324,"version":"3.30.2"},"reference-count":30,"publisher":"Elsevier BV","issue":"4-6","license":[{"start":{"date-parts":[[2003,9,1]],"date-time":"2003-09-01T00:00:00Z","timestamp":1062374400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2003,9]]},"DOI":"10.1016\/s1383-7621(03)00070-5","type":"journal-article","created":{"date-parts":[[2003,7,16]],"date-time":"2003-07-16T16:18:16Z","timestamp":1058372296000},"page":"227-246","source":"Crossref","is-referenced-by-count":18,"title":["Fast and compact sequential circuits for the FPGA-based reconfigurable systems"],"prefix":"10.1016","volume":"49","author":[{"given":"L.","family":"J\u00f3\u017awiak","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"\u015alusarczyk","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Chojnacki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(03)00070-5_BIB1","unstructured":"L. J\u00f3\u017awiak, M. Perkowski, D. Foote, Massively parallel structures of specialized reconfigurable cellular processors for fast symbolic computations, in: MPCS\u201998\u2013\u2013The Third International Conference on Massively Parallel Computing Systems, 1998, pp. 55\u201364"},{"issue":"3","key":"10.1016\/S1383-7621(03)00070-5_BIB2","doi-asserted-by":"crossref","first-page":"41","DOI":"10.1109\/MM.2002.1013303","article-title":"Learning hardware using multiple-valued logic\u2013\u2013part 1: Introduction and approach","volume":"2","author":"Perkowski","year":"2002","journal-title":"IEEE Micro"},{"issue":"3","key":"10.1016\/S1383-7621(03)00070-5_BIB3","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1109\/MM.2002.1013304","article-title":"Learning hardware using multiple-valued logic\u2013\u2013part 2: Cube calculus and architecture","volume":"2","author":"Perkowski","year":"2002","journal-title":"IEEE Micro"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB4","doi-asserted-by":"crossref","unstructured":"S.C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R.R. Taylor, R. Laufer, Piperench: a coprocessor for streaming multimedia acceleration, in: ISCA\u2013\u201326th International Symposium on Computer Architecture, 1999, pp. 28\u201339","DOI":"10.1109\/ISCA.1999.765937"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB5","doi-asserted-by":"crossref","unstructured":"A. Alsolaim, J. Becker, M. Glesner, J. Starzyk, Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems, in: Proceedings of FCCM\u201900, 2000, pp. 205\u2013216","DOI":"10.1109\/FPGA.2000.903407"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB6","unstructured":"D. Cherepacha, D. Levis, A datapath oriented architecture for fpgas, in: Proceedings of FPGA\u201994, 1994, pp. 1\u201311"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB7","doi-asserted-by":"crossref","unstructured":"J. Hauser, J. Wawrzynek, Garp: a mips processor with a reconfigurable coprocessor, in: Proceedings of FCCM\u201997, 1997, pp. 12\u201321","DOI":"10.1109\/FPGA.1997.624600"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB8","doi-asserted-by":"crossref","unstructured":"A. Marshall, T. Stansfield, I. Kostarnov, J. Vuillemin, B. Hutchings, A reconfigurable arithmetic array for multimedia applications, in: Proceedings of FPGA\u201998, 1998, pp. 135\u2013143","DOI":"10.1145\/296399.296444"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB9","doi-asserted-by":"crossref","unstructured":"J. Rabaey, Reconfigurable computing: the solution to low power pogrammable dsp, in: Proceedings of ICASSP\u201997, 1997, pp. 275\u2013278","DOI":"10.1109\/ICASSP.1997.599622"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB10","unstructured":"B. Lin, A.R. Newton, Synthesis of multiple level logic from symbolic high-level description languages, in: Proceedings of IFIP International Conference on VLSI, 1989, pp. 187\u2013196"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB11","doi-asserted-by":"crossref","unstructured":"E. Sentovich, K. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. Stephan, R. Brayton, A. Sangiovanni-Vincentelli, SIS: a system for sequential circuit synthesis, Memorandum No. UCB\/ERL M92\/41, University of California, Berkeley, 1992","DOI":"10.1109\/ICCD.1992.276282"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB12","doi-asserted-by":"crossref","unstructured":"L. J\u00f3\u017awiak, Information relationships and measures: an analysis apparatus for efficient information system synthesis, in: Proceedings of 23rd Euromicro Conference, 1997, pp. 13\u201323","DOI":"10.1109\/EURMIC.1997.617209"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB13","doi-asserted-by":"crossref","unstructured":"L. J\u00f3\u017awiak, Information relationship measures in application to logic design, in: Proceedings of ISMVL\u201999, 1999, pp. 228\u2013235","DOI":"10.1109\/ISMVL.1999.779721"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB14","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1109\/TCAD.1985.1270123","article-title":"Optimal state assignment for finite state machines","author":"de Micheli","year":"1985","journal-title":"IEEE Trans. CAD"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB15","unstructured":"E. BruceLee, M. Perkowski, Concurrent minimization and state assignment of finite state machines, in: Proceedings of International Conference on Systems, Man and Cybernetics, 1984, pp. 248\u2013260"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB16","doi-asserted-by":"crossref","unstructured":"M. Ciesielski, J. Shen, A unified approach to input\u2013output encoding for fsm state assignment, in: Proceedings of 28th DAC, 1991, pp. 176\u2013181","DOI":"10.1145\/127601.127659"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB17","doi-asserted-by":"crossref","unstructured":"M. Martinez, M. Avedillo, J. Quintana, J. Huertas, A dynamic model for the state assignment problem, in: Proceedings of DATE Conference, 1998, pp. 835\u2013839","DOI":"10.1109\/DATE.1998.655955"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB18","doi-asserted-by":"crossref","first-page":"905","DOI":"10.1109\/43.59068","article-title":"Nova: state assignment of finite state machines for optimal two-level logic implementation","author":"Villa","year":"1990","journal-title":"IEEE Trans. CAD"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB19","unstructured":"S. Devadas, H. Tony Ma, A. Newton, A. Sangiovanni-Vincentelli, Mustang: state assignment of finite state machines for optimal multi-level logic implementation, in: Proceedings of International Conference on CAD 1987, pp. 16\u201319"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB20","doi-asserted-by":"crossref","first-page":"28","DOI":"10.1109\/43.62789","article-title":"Muse: a multilevel symbolic encoding algorithm for state assignment","author":"Du","year":"1991","journal-title":"IEEE Trans. CAD"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB21","doi-asserted-by":"crossref","unstructured":"I. Lemberski, Modified approach to automata state encoding for lut-fpga implementation, in: Proceedings of 24th Euromicro Conference, 1998, pp. 196\u2013199","DOI":"10.1109\/EURMIC.1998.711798"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB22","doi-asserted-by":"crossref","unstructured":"C. Sarwary, E. Prado Lopes, L. Burgun, A. Greiner, Fsm synthesis on fpga architectures, in: Proceedings of 7th IEEE ASIC Conference, 1994, 178\u2013181","DOI":"10.1109\/ASIC.1994.404581"},{"year":"1966","series-title":"Algebraic Structure Theory of Sequential Machines","author":"Hartmanis","key":"10.1016\/S1383-7621(03)00070-5_BIB23"},{"year":"1992","series-title":"Sequential Logic Synthesis","author":"Ashar","key":"10.1016\/S1383-7621(03)00070-5_BIB24"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB25","doi-asserted-by":"crossref","first-page":"305","DOI":"10.1016\/0165-6074(90)90259-C","article-title":"Simultaneous decomposition of sequential machines","volume":"30","author":"J\u00f3\u017awiak","year":"1990","journal-title":"Microprocess. Microprog."},{"key":"10.1016\/S1383-7621(03)00070-5_BIB26","unstructured":"J. Shen, Z. Hasan, M. Ciesielski, State assignment for general fsm networks, in: Proceedings of EDAC, 1992, pp. 245\u2013249"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB27","doi-asserted-by":"crossref","unstructured":"J. Monteiro, J. Kukula, S. Devadas, H. Neto, Bitwise encoding of finite state machines, in: Proceedings of 7th Conference on VLSI Design, 1994, pp. 379\u2013382","DOI":"10.1109\/ICVD.1994.282723"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB28","unstructured":"L. J\u00f3\u017awiak, A. Chojnacki, Effective and efficient combinational circuit synthesis for the fpga-based reconfigurable systems, J. Syst. Architect., this issue"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB29","doi-asserted-by":"crossref","unstructured":"L. J\u00f3\u017awiak, A. Chojnacki, High-quality sub-function construction in functional decomposition based on information relationship measures, in: Proceedings of DATE\u201901 2001, pp. 383\u2013390","DOI":"10.1109\/DATE.2001.915053"},{"key":"10.1016\/S1383-7621(03)00070-5_BIB30","unstructured":"K. McElvain, IWLS\u201993 Benchmark Set: Version 4.0, Distributed as a part of IWLS\u201993 benchmark set, 1993"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762103000705?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762103000705?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2024,12,13]],"date-time":"2024-12-13T06:07:23Z","timestamp":1734070043000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762103000705"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,9]]},"references-count":30,"journal-issue":{"issue":"4-6","published-print":{"date-parts":[[2003,9]]}},"alternative-id":["S1383762103000705"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(03)00070-5","relation":{},"ISSN":["1383-7621"],"issn-type":[{"type":"print","value":"1383-7621"}],"subject":[],"published":{"date-parts":[[2003,9]]}}}