{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,4]],"date-time":"2022-04-04T02:42:48Z","timestamp":1649040168774},"reference-count":22,"publisher":"Elsevier BV","issue":"12-15","license":[{"start":{"date-parts":[[2003,12,1]],"date-time":"2003-12-01T00:00:00Z","timestamp":1070236800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2003,12]]},"DOI":"10.1016\/s1383-7621(03)00101-2","type":"journal-article","created":{"date-parts":[[2003,9,12]],"date-time":"2003-09-12T12:09:00Z","timestamp":1063368540000},"page":"619-639","source":"Crossref","is-referenced-by-count":6,"title":["A scalable single-chip multi-processor architecture with on-chip RTOS kernel"],"prefix":"10.1016","volume":"49","author":[{"given":"B.D.","family":"Theelen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.C.","family":"Verschueren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V.V.","family":"Reyes Su\u00e1rez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.P.J.","family":"Stevens","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Nu\u00f1ez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(03)00101-2_BIB1","first-page":"70","article-title":"Networks on chip: a new SoC paradigm","volume":"vol. 35(1)","author":"Benini","year":"2002"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB2","first-page":"82","article-title":"Are single-chip multiprocessors in reach?","volume":"vol. 18(1)","author":"Bergamaschi","year":"2001"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB3","series-title":"Proceedings of the Custom Integrated Circuits Conference","first-page":"623","article-title":"An efficient bus architecture for system-on-chip design","author":"Cordan","year":"1999"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB4","first-page":"46","article-title":"A scalable high-performance computing solution for networks on chips","volume":"vol. 22","author":"Forsell","year":"2002"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB5","series-title":"Processings of DATE\u201902","first-page":"423","article-title":"Networks on silicon: combining best-effort and guanranteed services","author":"Goossens","year":"2002"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB6","series-title":"The Cache Memory Book","author":"Handy","year":"1993"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB7","series-title":"IEEE Instrumentation and Measurement Magazine","first-page":"54","article-title":"Crafting a Java virtual machine in silicon","author":"Hardin","year":"2001"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB8","unstructured":"IBM, The Coreconnect Bus Architecture, coreconnect, White Paper, 1999. Available from http:\/\/www.chips.ibm.com\/products\/"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB9","unstructured":"IEE Computing and Control Devision: The T9000 Transputer, Colloqium 8, November 1994, IEE 1994, London, part of IEE colloqium digest IEE 1994-208"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB10","unstructured":"Intel Corp., Microprocessors Volume II, 1993, pp. 7-1\u20137-30 and 7-90\u20137-111 (ISBN 1-55512-170-5)"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB11","series-title":"Proceedings of the 38th Conference on Design Automation DAC","first-page":"518","article-title":"Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip","author":"Lyonnard","year":"2001"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB12","series-title":"Proceedings of the TRON Project International Symposium","first-page":"34","article-title":"Hardware implementation of a real-time operating system","author":"Nakano","year":"1995"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB13","unstructured":"A. Osborne, J. Kane, S. Jacobson, C. Ingraham, in: An Introduction to Microcomputers, vol. 2, Some Real Microprocessors, Adam Osborne and Associates, Berkeley, California, USA, 1978"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB14","series-title":"Proceedings of COMPCON\u201996","first-page":"319","article-title":"An architectual overview of the programmable multimedia processor TM-1","author":"Ratham","year":"1996"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB15","unstructured":"A.G. Siemens, in: Microcomputer Components Data Catalog, 1988, pp. 259\u2013260 (Document reference: B2-B3863-X-X-7600)"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB16","unstructured":"A.C. Verschueren, An object-oriented modelling technique for analysis and design of complex (real-time) systems, PhD thesis, Eindhoven University of Technology, Eindhoven, The Netherlands, 1992"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB17","series-title":"Proceedings of Euromicro\u201998, vol. 1","first-page":"42","article-title":"Rule base driven conversion of an object-oriented design data structure into standard hardware description languages","author":"Verschueren","year":"1998"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB18","series-title":"Proceedings of ProRISC\u201999","first-page":"563","article-title":"Arbitration in a multi-processor to multi-coprocessor connection switch","author":"Verschueren","year":"1999"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB19","unstructured":"A.C. Verschueren, IDaSS home page http:\/\/www.xs4all.nl\/\u223caverschu\/idass"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB20","unstructured":"Xilinx Inc. Spartan-II 2.5v FPGA Family: Introduction, November 2001 (Document reference: DS001-1 (v2.3))"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB21","unstructured":"Xilinx Inc. Spartan-II 2.5v FPGA Family: Functional Description, March 2001 (Document reference: DS001-2 (v2.1))"},{"key":"10.1016\/S1383-7621(03)00101-2_BIB22","unstructured":"Xilinx Inc. The WebPACK tool can be downloaded from http:\/\/www.xilinx.com"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762103001012?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762103001012?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,2,24]],"date-time":"2019-02-24T06:26:38Z","timestamp":1550989598000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762103001012"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2003,12]]},"references-count":22,"journal-issue":{"issue":"12-15","published-print":{"date-parts":[[2003,12]]}},"alternative-id":["S1383762103001012"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(03)00101-2","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2003,12]]}}}