{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,4,9]],"date-time":"2023-04-09T17:40:11Z","timestamp":1681062011103},"reference-count":18,"publisher":"Elsevier BV","issue":"8","license":[{"start":{"date-parts":[[1997,5,1]],"date-time":"1997-05-01T00:00:00Z","timestamp":862444800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[1997,5]]},"DOI":"10.1016\/s1383-7621(96)00123-3","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T15:21:35Z","timestamp":1027610495000},"page":"519-531","source":"Crossref","is-referenced-by-count":1,"title":["A partitioned on-chip virtual cache for fast processors"],"prefix":"10.1016","volume":"43","author":[{"given":"Dongwook","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joonwon","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Seungkyu","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"issue":"4","key":"10.1016\/S1383-7621(96)00123-3_bib1","doi-asserted-by":"crossref","first-page":"393","DOI":"10.1145\/48012.48037","article-title":"Cache performance of operating system and multiprogramming workloads","volume":"6","author":"Agarwal","year":"1988","journal-title":"ACM Trans. Comput. Systems"},{"key":"10.1016\/S1383-7621(96)00123-3_bib2","first-page":"179","article-title":"Column-associative caches: A technique for reducing the miss rate of direct-mapped caches","author":"Agarwal","year":"1993"},{"key":"10.1016\/S1383-7621(96)00123-3_bib3","first-page":"369","article-title":"Streamlining data cache access with fast address calculation","author":"Austin","year":"1995"},{"key":"10.1016\/S1383-7621(96)00123-3_bib4","series-title":"Proc. 1st Mach USENIX Workshop","first-page":"31","article-title":"Mach on a virtually addressed cache architecture","author":"Chao","year":"1990"},{"key":"10.1016\/S1383-7621(96)00123-3_bib5","series-title":"Proc. 1987 Summer USENIX Conf.","first-page":"217","article-title":"Virtual address cache in Unix","author":"Cheng","year":"1987"},{"key":"10.1016\/S1383-7621(96)00123-3_bib6","series-title":"Proc. 16th Ann. Internat. Symp. on Computer Architecture","first-page":"234","article-title":"Improving performance of small on-chip instruction caches","author":"Farrens","year":"1989"},{"key":"10.1016\/S1383-7621(96)00123-3_bib7","doi-asserted-by":"crossref","first-page":"72","DOI":"10.1145\/36206.36186","article-title":"Coherency for multiprocessor virtual address caches","author":"Goodman","year":"1987","journal-title":"ASPLOS-II"},{"key":"10.1016\/S1383-7621(96)00123-3_bib8","doi-asserted-by":"crossref","DOI":"10.21236\/ADA604007","article-title":"Aspects of cache memory and instruction buffer performance","author":"Hill","year":"1987"},{"issue":"12","key":"10.1016\/S1383-7621(96)00123-3_bib9","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/2.16187","article-title":"A case for direct-mapped caches","volume":"21","author":"Hill","year":"1988","journal-title":"IEEE Comput."},{"key":"10.1016\/S1383-7621(96)00123-3_bib10","series-title":"Proc. 17th Ann. Internat. Symp. on Computer Architecture","first-page":"364","article-title":"Improving direct-mapped cache performance by the addition of a small fully-associative cache prefetch buffers","author":"Jouppi","year":"1990"},{"key":"10.1016\/S1383-7621(96)00123-3_bib11","series-title":"Proc. 23th Ann. Internat. Symp. on Computer Architecture","first-page":"114","article-title":"The difference-bit cache","author":"Juan","year":"1996"},{"key":"10.1016\/S1383-7621(96)00123-3_bib12","series-title":"Proc. 18th Ann. Hawaii Internat. Conf. on System Sciences","first-page":"477","article-title":"Virtually addressed caches for multiprogramming and multiprocessing environments","author":"Knapp","year":"1985"},{"key":"10.1016\/S1383-7621(96)00123-3_bib13","series-title":"Proc. 4th Internat. Conf. on Architectural Supports for Programming Languages and Operating Systems","first-page":"75","article-title":"The effect of context switches on cache performance","author":"Mogul","year":"1991"},{"key":"10.1016\/S1383-7621(96)00123-3_bib14","article-title":"An enhanced access and cycle time model for on-chip caches","volume":"93\/5","author":"Wilton","year":"1994","journal-title":"WRL Research Rept."},{"key":"10.1016\/S1383-7621(96)00123-3_bib15","series-title":"Proc. 15th Ann. Internat. Symp. on Computer Architecture","first-page":"290","article-title":"Performance tradeoffs in cache design","author":"Prizybylski","year":"1988"},{"key":"10.1016\/S1383-7621(96)00123-3_bib16","series-title":"Proc. 16th Ann. Internat. Symp. on Computer Architecture","first-page":"140","article-title":"Organization and performance of a two level virtual real cache hierarchy","author":"Wang","year":"1989"},{"key":"10.1016\/S1383-7621(96)00123-3_bib17","series-title":"Proc. 5th Internat. Conf. on Architectural Support for Programming Languages and Operating Systems","first-page":"124","article-title":"Consistency management for virtually indexed caches","author":"Wheeler","year":"1992"},{"issue":"10","key":"10.1016\/S1383-7621(96)00123-3_bib18","doi-asserted-by":"crossref","first-page":"1154","DOI":"10.1109\/12.257701","article-title":"A quantative evaluation of cache types for high-performance computer systems","volume":"42","author":"Wu","year":"1993","journal-title":"IEEE Trans. Comput."}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762196001233?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762196001233?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2023,4,9]],"date-time":"2023-04-09T17:21:52Z","timestamp":1681060912000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762196001233"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,5]]},"references-count":18,"journal-issue":{"issue":"8","published-print":{"date-parts":[[1997,5]]}},"alternative-id":["S1383762196001233"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(96)00123-3","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[1997,5]]}}}