{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T21:25:05Z","timestamp":1762032305049},"reference-count":21,"publisher":"Elsevier BV","issue":"9-10","license":[{"start":{"date-parts":[[1998,6,1]],"date-time":"1998-06-01T00:00:00Z","timestamp":896659200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[1998,6]]},"DOI":"10.1016\/s1383-7621(97)00012-x","type":"journal-article","created":{"date-parts":[[2002,7,25]],"date-time":"2002-07-25T18:26:53Z","timestamp":1027621613000},"page":"657-674","source":"Crossref","is-referenced-by-count":6,"title":["Design of cache memories for dataflow architecture"],"prefix":"10.1016","volume":"44","author":[{"given":"Krishna M.","family":"Kavi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.R.","family":"Hurson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(97)00012-X_bib1","series-title":"Proceedings of the 16th Annual International Symposium on Computer Architecture","first-page":"262","article-title":"Can Dataflow subsume von neumann computing?","author":"Arvind","year":"1989"},{"issue":"3","key":"10.1016\/S1383-7621(97)00012-X_bib2","doi-asserted-by":"crossref","first-page":"347","DOI":"10.1006\/jpdc.1993.1070","article-title":"TAM \u2014 a compiler controlled threaded abstract machine","volume":"18","author":"Culler","year":"1993","journal-title":"J. Parallel Distrib. Comput."},{"issue":"3","key":"10.1016\/S1383-7621(97)00012-X_bib3","doi-asserted-by":"crossref","first-page":"273","DOI":"10.1006\/jpdc.1993.1065","article-title":"Performance studies of the monsoon dataflow processor","volume":"18","author":"Hicks","year":"1993","journal-title":"J. Parallel Distrib. Comput."},{"key":"10.1016\/S1383-7621(97)00012-X_bib4","series-title":"Proceedings of the International Symposium on Computer Architecture","first-page":"131","article-title":"Toward a Dataflow\/von Neumann Hybrid Architecture","author":"Ianucci","year":"1988"},{"key":"10.1016\/S1383-7621(97)00012-X_bib5","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1109\/2.303620","article-title":"Dataflow Architectures and Multithreading","author":"Lee","year":"1994","journal-title":"IEEE Computer"},{"key":"10.1016\/S1383-7621(97)00012-X_bib6","series-title":"The 17th Annual International Symposium on Computer Architecture","first-page":"82","article-title":"An explicit token-Store architecture","author":"Papadopolous","year":"1990"},{"key":"10.1016\/S1383-7621(97)00012-X_bib7","series-title":"Implementation of a General Purpose Dataflow Multiprocessor","author":"Papadopolous","year":"1991"},{"key":"10.1016\/S1383-7621(97)00012-X_bib8","series-title":"Proceedings of the 22nd International Symposium on Computer Architecture","first-page":"253","article-title":"Design of cache memories for multithreaded dataflow architecture","author":"Kavi","year":"1995"},{"key":"10.1016\/S1383-7621(97)00012-X_bib9","doi-asserted-by":"crossref","first-page":"15","DOI":"10.1109\/2.318580","article-title":"Cache Profiling and the SPEC Benchmarks: A Case Study","author":"Lebeck","year":"1994","journal-title":"IEEE Computer"},{"key":"10.1016\/S1383-7621(97)00012-X_bib10","article-title":"Cache and Memory Hierarchy Design: A Performance-Directed Approach","author":"Przybylski","year":"1990"},{"key":"10.1016\/S1383-7621(97)00012-X_bib11","doi-asserted-by":"crossref","first-page":"473","DOI":"10.1145\/356887.356892","article-title":"Cache Memories","author":"Smith","year":"1982","journal-title":"ACM Computing Surveys"},{"key":"10.1016\/S1383-7621(97)00012-X_bib12","article-title":"The Cache Coherence Problem in Shared-Memory Multiprocessors","author":"Tartalja","year":"1996"},{"key":"10.1016\/S1383-7621(97)00012-X_bib13","series-title":"Proceedings of the 10th Annual International Symposium on Computer Architecture","first-page":"90","article-title":"On the working set concept for data-flow machines","author":"Tokoro","year":"1987"},{"key":"10.1016\/S1383-7621(97)00012-X_bib14","series-title":"Proceedings of the International Conference on Parallel Conference","first-page":"356","article-title":"A feasibility study of a memory hierarchy in data flow environment","author":"Thoreson","year":"1987"},{"key":"10.1016\/S1383-7621(97)00012-X_bib15","series-title":"Proceedings of the 14th Annual International Symposium on Computer Architecture","first-page":"90","article-title":"A unified resource management and execution control mechanism for dataflow machines","author":"Takesue","year":"1987"},{"issue":"6","key":"10.1016\/S1383-7621(97)00012-X_bib16","doi-asserted-by":"crossref","first-page":"667","DOI":"10.1109\/12.144620","article-title":"Cache memories for data flow architectures","volume":"41","author":"Takesue","year":"1992","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S1383-7621(97)00012-X_bib17","doi-asserted-by":"crossref","first-page":"1612","DOI":"10.1109\/12.40842","article-title":"Evaluating associativity of CPU caches","volume":"vol. 38","author":"Hill","year":"1989","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S1383-7621(97)00012-X_bib18","series-title":"Proceedings of the 26th Hawaii International Conference On System Sciences","first-page":"487","article-title":"Program partitioning for multithreaded dataflow computers","author":"Lee","year":"1993"},{"key":"10.1016\/S1383-7621(97)00012-X_bib19","doi-asserted-by":"crossref","first-page":"225","DOI":"10.1146\/annurev.cs.01.060186.001301","article-title":"Dataflow Architectures","volume":"1","author":"Arvind","year":"1986","journal-title":"Annual Rev. Comput. Sci."},{"key":"10.1016\/S1383-7621(97)00012-X_bib20","doi-asserted-by":"crossref","first-page":"349","DOI":"10.1016\/0743-7315(90)90035-N","article-title":"A report on Sisal language project","volume":"vol. 10","author":"Feo","year":"1990","journal-title":"J. Parallel Distrib. Comput."},{"key":"10.1016\/S1383-7621(97)00012-X_bib21","series-title":"Proceeding of the 22nd International Symposium on Computer Architecture","first-page":"392","article-title":"Simultaneous multithreading: Maximizing on chip parallelism","author":"Tullsen","year":"1995"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S138376219700012X?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S138376219700012X?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,4,19]],"date-time":"2019-04-19T01:59:14Z","timestamp":1555639154000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S138376219700012X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1998,6]]},"references-count":21,"journal-issue":{"issue":"9-10","published-print":{"date-parts":[[1998,6]]}},"alternative-id":["S138376219700012X"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(97)00012-x","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[1998,6]]}}}