{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,6]],"date-time":"2024-12-06T05:25:04Z","timestamp":1733462704372,"version":"3.30.1"},"reference-count":44,"publisher":"Elsevier BV","issue":"9","license":[{"start":{"date-parts":[[1999,3,1]],"date-time":"1999-03-01T00:00:00Z","timestamp":920246400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[1999,3]]},"DOI":"10.1016\/s1383-7621(98)00009-5","type":"journal-article","created":{"date-parts":[[2003,4,7]],"date-time":"2003-04-07T18:33:56Z","timestamp":1049740436000},"page":"651-679","source":"Crossref","is-referenced-by-count":0,"title":["The Precomputed-Branch architecture: Efficient branches with compiler support"],"prefix":"10.1016","volume":"45","author":[{"given":"Brad","family":"Calder","sequence":"first","affiliation":[]},{"given":"Dirk","family":"Grunwald","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"issue":"5","key":"10.1016\/S1383-7621(98)00009-5_BIB1","doi-asserted-by":"crossref","first-page":"341","DOI":"10.1109\/TC.1981.1675792","article-title":"On the performance enhancement of paging systems through program analysis and transformation","volume":"C","author":"Abu-Sufah","year":"1981","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB2","doi-asserted-by":"crossref","unstructured":"J.L. Baer, R. Caughey, Segmentation and optimization of programs from Cyclic Structure Analysis, in: Proceedings of AFIPS, 1972, pp. 23\u201336","DOI":"10.1145\/1478873.1478877"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB3","doi-asserted-by":"crossref","unstructured":"T. Ball, J.R. Larus, Branch prediction for free, in: 1993 SIGPLAN Conference on Programming Language Design and Implementation, ACM, June 1993, pp. 300\u2013313","DOI":"10.1145\/155090.155119"},{"issue":"3","key":"10.1016\/S1383-7621(98)00009-5_BIB4","doi-asserted-by":"crossref","first-page":"5","DOI":"10.1177\/109434208900300302","article-title":"The perfect club benchmarks: Effective performance evaluation of supercomputers","volume":"3","author":"Berry","year":"1989","journal-title":"The International Journal of Supercomputer Applications"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB5","doi-asserted-by":"crossref","unstructured":"B. Calder, D. Grunwald, Fast & accurate instruction fetch and branch prediction, in: 21st Annual International Symposium of Computer Architecture, ACM, April 1994, pp. 2\u201311","DOI":"10.1109\/ISCA.1994.288166"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB6","doi-asserted-by":"crossref","unstructured":"B. Calder, D. Grunwald, Reducing branch costs via branch alignment, in: Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, 1994, pp. 242\u2013251","DOI":"10.1145\/195473.195553"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB7","doi-asserted-by":"crossref","unstructured":"B. Calder, D. Grunwald, Reducing indirect function call overhead in C++ programs, in: Proceedings of the 21st Annual ACM Symposium on Principles of Programming Languages, January 1994, pp. 397\u2013408","DOI":"10.1145\/174675.177973"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB8","doi-asserted-by":"crossref","unstructured":"B. Calder, D. Grunwald, Next cache line and set prediction, in: 22nd Annual International Symposium of Computer Architecture, ACM, June 1995, pp. 287\u2013296","DOI":"10.1145\/223982.224439"},{"issue":"1","key":"10.1016\/S1383-7621(98)00009-5_BIB9","doi-asserted-by":"crossref","first-page":"188","DOI":"10.1145\/239912.239923","article-title":"Evidence-based static branch prediction using machine learning","volume":"19","author":"Calder","year":"1997","journal-title":"ACM Transactions on Programming Languages and Systems"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB10","doi-asserted-by":"crossref","unstructured":"B. Calder, D. Grunwald, A. Srivastava, The predictability of branches in libraries, in: 28th International Symposium on Microarchitecture, IEEE, Ann Arbor, MI, November 1995, pp. 24\u201334","DOI":"10.1109\/MICRO.1995.476808"},{"issue":"4","key":"10.1016\/S1383-7621(98)00009-5_BIB11","first-page":"313","article-title":"Quantifying behavioral differences between C and C++ programs","volume":"2","author":"Calder","year":"1994","journal-title":"Journal of Programming Languages"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB12","doi-asserted-by":"crossref","unstructured":"D.R. Ditzel, H.R. McLellan, Branch folding in the CRISP microprocessor: Reducing branch delay to zero, in: 14th Annual International Symposium of Computer Architecture, ACM, June 1987, pp. 2\u20139","DOI":"10.1145\/30350.30351"},{"issue":"11","key":"10.1016\/S1383-7621(98)00009-5_BIB13","doi-asserted-by":"crossref","first-page":"614","DOI":"10.1145\/361179.361195","article-title":"Improving locality by critical working sets","volume":"17","author":"Ferrari","year":"1974","journal-title":"Communications of the ACM"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB14","doi-asserted-by":"crossref","unstructured":"J.A. Fisher, S.M. Freudenberger, Predicting conditional branch directions from previous runs of a program, in: Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, Boston, Massachusetts, October 1992, pp. 85\u201395","DOI":"10.1145\/143365.143493"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB15","doi-asserted-by":"crossref","unstructured":"N. Gloy, T. Blackwell, M.D. Smith, B. Calder, Procedure placement using temporal ordering information, in: 30th International Symposium on Microarchitecture, December 1997, pp. 303\u2013313","DOI":"10.1109\/MICRO.1997.645824"},{"issue":"11","key":"10.1016\/S1383-7621(98)00009-5_BIB16","doi-asserted-by":"crossref","first-page":"1640","DOI":"10.1109\/32.9051","article-title":"Compile-time program restructuring in multiprogrammed virtual memory systems","volume":"14","author":"Hartley","year":"1988","journal-title":"IEEE Transactions on Software Engineering"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB17","doi-asserted-by":"crossref","unstructured":"A. Hashemi, D.R. Kaeli, B. Calder, Efficient procedure mapping using cache line coloring, in: Proceedings of the ACM SIGPLAN '97 Conference on Programming Language Design and Implementation, June 1997, pp. 171\u2013182","DOI":"10.1145\/258915.258931"},{"issue":"12","key":"10.1016\/S1383-7621(98)00009-5_BIB18","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/2.16187","article-title":"A case for direct-mapped caches","volume":"21","author":"Hill","year":"1988","journal-title":"IEEE Computer"},{"issue":"2","key":"10.1016\/S1383-7621(98)00009-5_BIB19","doi-asserted-by":"crossref","first-page":"23","DOI":"10.1109\/40.272835","article-title":"Designing the TFP microprocessor","volume":"14","author":"Hsu","year":"1994","journal-title":"IEEE Micro"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB20","doi-asserted-by":"crossref","unstructured":"W.W. Hwu, P.P. Chang, Achieving high instruction cache performance with an optimizing compiler, in: 168th Annual International Symposium of Computer Architecture, ACM, 1989, pp. 242\u2013251","DOI":"10.1145\/74925.74953"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB21","doi-asserted-by":"crossref","unstructured":"D.R. Kaeli, P.G. Emma, Branch history table prediction of moving target branches due to subroutine returns, in: 18th Annual International Symposium of Computer Architecture, ACM, May 1991, pp. 34\u201342","DOI":"10.1145\/115952.115957"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB22","unstructured":"M.G.H. Katevenis, Reduced instruction set computer architecture for VLSI, ACM Doctoral Dissertation Award Series, MIT Press, Cambridge, MA, 1985"},{"issue":"7","key":"10.1016\/S1383-7621(98)00009-5_BIB23","doi-asserted-by":"crossref","first-page":"6","DOI":"10.1109\/MC.1984.1658927","article-title":"Branch prediction strategies and branch target buffer design","volume":"21","author":"Lee","year":"1984","journal-title":"IEEE Computer"},{"issue":"7","key":"10.1016\/S1383-7621(98)00009-5_BIB24","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1109\/2.68","article-title":"Reducing the branch penalty in pipelined processors","volume":"21","author":"Lilja","year":"1988","journal-title":"IEEE Computer"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB25","unstructured":"S. McFarling, Combining branch predictors, TN 36, DEC-WRL, June 1993"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB26","doi-asserted-by":"crossref","unstructured":"S. McFarling, J. Hennessy, Reducing the cost of branches, in: 13th Annual International Symposium of Computer Architecture, ACM, 1986, pp. 396\u2013403","DOI":"10.1145\/17356.17402"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB27","unstructured":"MIPS Technologies Inc., R10000 microprocessor product overview, Technical report, MIPS Technologies Inc. (1994)"},{"issue":"2","key":"10.1016\/S1383-7621(98)00009-5_BIB28","doi-asserted-by":"crossref","first-page":"98","DOI":"10.1109\/4.68123","article-title":"An area model for on-chip memories and its application","volume":"26","author":"Mulder","year":"1991","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB29","doi-asserted-by":"crossref","unstructured":"S.T. Pan, K. So, J.T. Rahmeh, Improving the accuracy of dynamic branch prediction using branch correlation, in: Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, ACM, Boston, Massachusetts, October 1992","DOI":"10.1145\/143365.143490"},{"issue":"4","key":"10.1016\/S1383-7621(98)00009-5_BIB30","doi-asserted-by":"crossref","first-page":"396","DOI":"10.1109\/12.214687","article-title":"Branch target buffer design and optimization","volume":"42","author":"Perleberg","year":"1993","journal-title":"IEEE Transactions on Computers"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB31","doi-asserted-by":"crossref","unstructured":"K. Pettis, R.C. Hansen, Profile guided code positioning, in: Proceedings of the ACM SIGPLAN '90 Conference on Programming Language Design and Implementation, ACM, June 1990, pp. 16\u201327","DOI":"10.1145\/93542.93550"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB32","doi-asserted-by":"crossref","unstructured":"S. Przybylski, M. Horowitz, J. Hennesy, Characteristics of performance-optimal multi-level cache hierarchy, in: 168th Annual International Symposium of Computer Architecture, IEEE, 1989, pp. 114\u2013121","DOI":"10.1109\/ISCA.1989.714545"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB33","unstructured":"J.E. Smith, A study of branch prediction strategies, in: 8th Annual International Symposium of Computer Architecture, ACM, 1981, pp. 135\u2013148"},{"issue":"5","key":"10.1016\/S1383-7621(98)00009-5_BIB34","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1109\/MM.1994.363071","article-title":"The PowerPC 604 RISC microprocessor","volume":"14","author":"Song","year":"1994","journal-title":"IEEE Micro"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB35","doi-asserted-by":"crossref","unstructured":"A. Srivastava, A. Eustace, ATOM: A system for building customized program analysis tools, in: 1994 Programming Language Design and Implementation, ACM, June 1994, pp. 196\u2013205","DOI":"10.1145\/178243.178260"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB36","unstructured":"A. Srivastava, D.W. Wall, A practical system for intermodule code optimizations at link-time, Journal of Programming Languages, March 1992 (Also available as DEC-WRL TR-92-6)"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB37","doi-asserted-by":"crossref","unstructured":"T.A. Wagner, V. Maverick, S. Graham, M. Harrison, Accurate static estimators for program optimization, in: Proceedings of the SIGPLAN'94 Conference on Programming Language Design and Implementation, ACM, Orlando, Florida, June 1994, pp. 85\u201396","DOI":"10.1145\/178243.178251"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB38","doi-asserted-by":"crossref","unstructured":"D.W. Wall, Limits of instruction-level parallelism, in: Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, 1991, pp. 176\u2013188","DOI":"10.1145\/106972.106991"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB39","unstructured":"S.J.E. Wilton, N.P. Jouppi, An enhanced access and cycle time model for on-chip caches, Report 93\/5, DEC Western Research Lab (1993)"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB40","doi-asserted-by":"crossref","unstructured":"Y. Wu, J.R. Larus, Static branch frequency and program profile analysis, in: 27th International Symposium on Microarchitecture, IEEE, San Jose, CA, November 1994","DOI":"10.1145\/192724.192725"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB41","doi-asserted-by":"crossref","unstructured":"T. Yeh, Y.N. Patt, Alternative implementations of two-level adaptive branch predictions, in: 19th Annual International Symposium of Computer Architecture, Gold Coast, Australia, ACM, May 1992, pp. 124\u2013134","DOI":"10.1145\/139669.139709"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB42","doi-asserted-by":"crossref","unstructured":"T. Yeh, Y.N. Patt, A comprehensive instruction fetch mechanism for a processor supporting speculative execution, in: 25th International Symposium on Microarchitecture, ACM, Portland, OR, December 1992, pp. 129\u2013139","DOI":"10.1145\/144965.145016"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB43","doi-asserted-by":"crossref","unstructured":"T. Yeh, Y.N. Patt, A comparison of dynamic branch predictors that use two levels of branch history, in: 20th Annual International Symposium of Computer Architecture, ACM, San Diego, CA, May 1993, pp. 257\u2013266","DOI":"10.1145\/165123.165161"},{"key":"10.1016\/S1383-7621(98)00009-5_BIB44","doi-asserted-by":"crossref","unstructured":"C. Young, M.D. Smith, Improving the accuracy of static branch prediction using branch correlation, in: Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, October 1994, pp. 232\u2013241","DOI":"10.1145\/195473.195549"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762198000095?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762198000095?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2024,12,6]],"date-time":"2024-12-06T00:48:46Z","timestamp":1733446126000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762198000095"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,3]]},"references-count":44,"journal-issue":{"issue":"9","published-print":{"date-parts":[[1999,3]]}},"alternative-id":["S1383762198000095"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(98)00009-5","relation":{},"ISSN":["1383-7621"],"issn-type":[{"type":"print","value":"1383-7621"}],"subject":[],"published":{"date-parts":[[1999,3]]}}}