{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T13:19:13Z","timestamp":1761311953796,"version":"build-2065373602"},"reference-count":29,"publisher":"Elsevier BV","issue":"12-13","license":[{"start":{"date-parts":[[1999,6,1]],"date-time":"1999-06-01T00:00:00Z","timestamp":928195200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"},{"start":{"date-parts":[[1999,6,1]],"date-time":"1999-06-01T00:00:00Z","timestamp":928195200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/legal\/tdmrep-license"},{"start":{"date-parts":[[2001,6,6]],"date-time":"2001-06-06T00:00:00Z","timestamp":991785600000},"content-version":"vor","delay-in-days":736,"URL":"http:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"content-domain":{"domain":["elsevier.com","sciencedirect.com"],"crossmark-restriction":true},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[1999,6]]},"DOI":"10.1016\/s1383-7621(98)00052-6","type":"journal-article","created":{"date-parts":[[2003,4,7]],"date-time":"2003-04-07T14:33:56Z","timestamp":1049726036000},"page":"1097-1110","update-policy":"https:\/\/doi.org\/10.1016\/elsevier_cm_policy","source":"Crossref","is-referenced-by-count":2,"title":["STATS: A framework for microprocessor and system-level design space exploration"],"prefix":"10.1016","volume":"45","author":[{"given":"David","family":"H. Albonesi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Israel","family":"Koren","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(98)00052-6_BIB1","doi-asserted-by":"crossref","unstructured":"D.H. Albonesi, I. Koren, Architecture and technology tradeoffs in the design of next-generation multiprocessor servers, Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995, pp. 174\u2013181","DOI":"10.1109\/SPDP.1995.530681"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB2","unstructured":"D.H. Albonesi, Architecture and technology tradeoffs in the design of high performance microprocessor-based systems, PhD Thesis, University of Massachusetts, Amherst, MA, 1996"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB3","doi-asserted-by":"crossref","unstructured":"S.P. Amarasinghe et al., Multiprocessors from a Software Perspective, IEEE Micro 16 (3) (1996) 52\u201361","DOI":"10.1109\/40.502406"},{"issue":"12","key":"10.1016\/S1383-7621(98)00052-6_BIB4","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1109\/2.476200","article-title":"A visualization-based microarchitecture workbench","volume":"28","author":"Diep","year":"1995","journal-title":"IEEE Computer"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB5","unstructured":"Digital Equipment Corporation, Alpha 21064A Microprocessor Product Brief, March 1995"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB6","unstructured":"J.H. Edmondson et al., Internal organization of the alpha 21164, a 300MHz 64-bit quad-issue CMOS RISC microprocessor (special issue), Digital Technical Journal 7 (1) (1995) 119\u2013135"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB7","doi-asserted-by":"crossref","unstructured":"J.D. Gee et al., Cache performance of the SPEC92 benchmark suite, IEEE Micro 13 (4) (1993) 17\u201327","DOI":"10.1109\/40.229711"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB8","doi-asserted-by":"crossref","unstructured":"T. Hara, H. Ando, C. Nakanishi, M. Nakaya, Performance comparison of ILP machines with cycle time evaluation, Proceeding of the 23rd International Symposium on Computer Architecture, 1996, pp. 213\u2013224","DOI":"10.1145\/232973.232995"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB9","doi-asserted-by":"crossref","unstructured":"R. Jog, P.L. Vitale, J.R. Callister, Performance evaluation of a commercial cache-coherent shared memory multiprocessor, Proceedings of SIGMETRICS, 1990, 173\u2013182","DOI":"10.1145\/98460.98756"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB10","unstructured":"W.M. Johnson, Superscalar Microprocessor Design, Prentice-Hall, Englewood Cliffs, NJ, 1991"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB11","doi-asserted-by":"crossref","unstructured":"N.P. Jouppi, S.J.E. Wilton, Tradeoffs in two-level on-chip caching, Proceedings of the 21st International Symposium on Computer Architecture, 1994, 34\u201345","DOI":"10.1109\/ISCA.1994.288163"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB12","doi-asserted-by":"crossref","unstructured":"S. Jourdan, P. Sainrat, D. Litaize, Exploring configurations of functional units in an out-of-order superscalar processor, Proceedings of the 22nd International Symposium on Computer Architecture, 1995, 117\u2013125","DOI":"10.1145\/223982.224366"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB13","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1007\/BF01205182","article-title":"The multiflow trace scheduling compiler","volume":"7","author":"Lowney et al","year":"1993","journal-title":"Journal of Supercomputing"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB14","unstructured":"Motorola Inc. MCM36804 8M\u00d736 bit static random access memory module product data sheet, 1995"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB15","unstructured":"Motorola Inc. MCM6709BR 64k\u00d74 bit static random access memory product data sheet, 1995"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB16","unstructured":"Motorola Inc. MCM6706CR 32k\u00d78 bit static random access memory product data sheet, 1995"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB17","unstructured":"Motorola Inc. MCM6726C 128k\u00d78 bit static random access memory product data sheet, 1995"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB18","doi-asserted-by":"crossref","unstructured":"O.A. Olukotun et al., Multilevel optimization in the design of a high-performance GaAs microcomputer, IEEE Journal of Solid State Circuits 26 (5) (1991) 763\u2013767","DOI":"10.1109\/4.78246"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB19","doi-asserted-by":"crossref","unstructured":"K. Olukotun, T. Mudge, R. Brown, Performance Optimization for Pipelined Primary Caches, Proceedings of the 19th International Symposium on Computer Architecture, 1992, pp. 181\u2013190","DOI":"10.1109\/ISCA.1992.753315"},{"issue":"6","key":"10.1016\/S1383-7621(98)00052-6_BIB20","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1145\/175208.175214","article-title":"The PowerPC performance modeling methodology","volume":"37","author":"Poursepanj","year":"1994","journal-title":"Communications of the ACM"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB21","doi-asserted-by":"crossref","unstructured":"M. Simone et al., Implementation trade-offs in using a restricted data flow architecture in a high performance RISC microprocessor, Proceedings of the 22nd International Symposium on Computer Architecture, 1995, pp. 151\u2013162","DOI":"10.1145\/223982.224411"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB22","unstructured":"T.J. Stanley, T. Mudge, A parallel genetic algorithm for multiobjective microprocessor design, Proceedings of the 6th International Conference on Genetic Algorithms, July 1995"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB23","doi-asserted-by":"crossref","unstructured":"T.J. Stanley, T. Mudge, Systematic objective-driven computer technology optimization, Proceedings of the 16th Conference on Advanced Research in VLSI, 1995, pp. 286\u2013300","DOI":"10.1109\/ARVLSI.1995.515627"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB24","doi-asserted-by":"crossref","unstructured":"R. Uhlig et al., Instruction fetching: Coping with code bloat, Proceedings of the 22nd International Symposium on Computer Architecture, 1995, pp. 345\u2013356","DOI":"10.1145\/223982.224445"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB25","doi-asserted-by":"crossref","unstructured":"M. Upton et al., Resource allocation in a high clock rate microprocessor, Proceedings of ASPLOS-VI, 1994, pp. 98\u2013109","DOI":"10.1145\/195473.195510"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB26","doi-asserted-by":"crossref","unstructured":"M.K. Vernon, E.D. Lazowska, J. Zahorjan, An accurate and efficient performance analysis technique for multiprocessor snooping cache consistency protocols, Proceedings of the 15th International Symposium on Computer Architecture, 1988, pp. 308\u2013315","DOI":"10.1109\/ISCA.1988.5241"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB27","doi-asserted-by":"crossref","unstructured":"B.P. Wilson et al., SUIF: A parallelizing and optimizing research compiler, ACM SIGPLAN Notices 29 (12) 1994 31\u201337","DOI":"10.1145\/193209.193217"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB28","doi-asserted-by":"crossref","unstructured":"K.M. Wilson, K. Olukotun, M. Rosenblum, Increasing cache port efficiency for dynamic superscalar microprocessors, Proceeding of the 23rd International Symposium on Computer Architecture, 1996, pp. 147\u2013157","DOI":"10.1145\/232973.232989"},{"key":"10.1016\/S1383-7621(98)00052-6_BIB29","unstructured":"S.J.E. Wilton, N.P. Jouppi, An enhanced access and cycle time model for on-chip caches, Technical Report 93\/5, Digital Western Research Laboratory, July 1994"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762198000526?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762198000526?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T13:16:26Z","timestamp":1761311786000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762198000526"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1999,6]]},"references-count":29,"journal-issue":{"issue":"12-13","published-print":{"date-parts":[[1999,6]]}},"alternative-id":["S1383762198000526"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(98)00052-6","relation":{},"ISSN":["1383-7621"],"issn-type":[{"type":"print","value":"1383-7621"}],"subject":[],"published":{"date-parts":[[1999,6]]},"assertion":[{"value":"Elsevier","name":"publisher","label":"This article is maintained by"},{"value":"STATS: A framework for microprocessor and system-level design space exploration","name":"articletitle","label":"Article Title"},{"value":"Journal of Systems Architecture","name":"journaltitle","label":"Journal Title"},{"value":"https:\/\/doi.org\/10.1016\/S1383-7621(98)00052-6","name":"articlelink","label":"CrossRef DOI link to publisher maintained version"},{"value":"converted-article","name":"content_type","label":"Content Type"},{"value":"Copyright \u00a9 1999 Elsevier Science B.V. All rights reserved.","name":"copyright","label":"Copyright"}]}}