{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T10:25:19Z","timestamp":1649154319090},"reference-count":20,"publisher":"Elsevier BV","issue":"5","license":[{"start":{"date-parts":[[2000,3,1]],"date-time":"2000-03-01T00:00:00Z","timestamp":951868800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2000,3]]},"DOI":"10.1016\/s1383-7621(99)00021-1","type":"journal-article","created":{"date-parts":[[2003,4,4]],"date-time":"2003-04-04T21:09:52Z","timestamp":1049490592000},"page":"439-454","source":"Crossref","is-referenced-by-count":0,"title":["Improving cache performance with Full-Map Block Directory"],"prefix":"10.1016","volume":"46","author":[{"given":"Jih-Kwon","family":"Peir","sequence":"first","affiliation":[]},{"given":"Windsor W.","family":"Hsu","sequence":"additional","affiliation":[]},{"given":"Honesty","family":"Young","sequence":"additional","affiliation":[]},{"given":"Shauchi","family":"Ong","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"issue":"4","key":"10.1016\/S1383-7621(99)00021-1_BIB1","doi-asserted-by":"crossref","first-page":"393","DOI":"10.1145\/48012.48037","article-title":"Cache performance of operating systems and multiprogramming","volume":"6","author":"Agarwal","year":"1988","journal-title":"ACM Trans. Comput. Syst."},{"key":"10.1016\/S1383-7621(99)00021-1_BIB2","doi-asserted-by":"crossref","unstructured":"A. Agarwal, S. Pudar, Column-associative caches: a technique for reducing the miss rate of direct-mapped caches, in: Proceedings of the 20th International Symposium on Computer Architecture, 1993, pp. 179\u2013190","DOI":"10.1145\/165123.165153"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB3","doi-asserted-by":"crossref","unstructured":"B. Calder, D. Grunwald, J. Emer, Predictive sequential associative cache, in: Proceedings of the Second Symposium on High-Performance Computer Architecture, 1996, pp. 244\u2013253","DOI":"10.1109\/HPCA.1996.501190"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB4","doi-asserted-by":"crossref","unstructured":"N. Drach, A. Seznec, Semi-unified caches, in: Proceedings of the 1993 International Conference on Parallel Processing, 1993, pp. 25\u201328","DOI":"10.1109\/ICPP.1993.162"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB5","unstructured":"J. Hennessy, D. Patterson, Computer Architecture, A Quantitative Approach, 2nd ed., Morgan-Kaufmann, Los Altos, 1996"},{"issue":"12","key":"10.1016\/S1383-7621(99)00021-1_BIB6","doi-asserted-by":"crossref","first-page":"25","DOI":"10.1109\/2.16187","article-title":"A case for direct-mapped caches","volume":"21","author":"Hill","year":"1988","journal-title":"IEEE Comput."},{"key":"10.1016\/S1383-7621(99)00021-1_BIB7","doi-asserted-by":"crossref","unstructured":"K. Hua, A. Hunt, L. Liu, J.-K. Peir, D. Pruett, J. Temple, Early resolution of address translation in cache design, in: Proceedings of the International Conference on Computer Designs, 1990, pp. 408\u2013412","DOI":"10.1109\/ICCD.1990.130264"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB8","doi-asserted-by":"crossref","unstructured":"N. Jouppi, S. Wilton, Tradeoffs in two-level on-chip caching, in: Proceedings of the 21st International Symposium on Computer Architecture, 1994, pp. 34\u201345","DOI":"10.1109\/ISCA.1994.288163"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB9","doi-asserted-by":"crossref","unstructured":"T. Juan, T. Lang, J. Navarro, The difference-bit cache, in: Proceedings of the 23rd International Symposium on Computer Architecture, 1996, pp. 114\u2013120","DOI":"10.1145\/232973.232986"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB10","doi-asserted-by":"crossref","unstructured":"R. Kessler, R. Jooss, A Lebeck, M. Hill, Inexpensive implementation of set-associativity, in: Proceedings of the 16th International Symposium on Computer Architecture, 1988","DOI":"10.1145\/74925.74941"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB11","doi-asserted-by":"crossref","unstructured":"D. Levitan, T. Thomas, P. Tu, The PowerPC 620 microprocessor: a high performance superscalar RISC microprocessor, in: Proceedings of the COMPCON'95, 1995, pp. 285\u2013291","DOI":"10.1109\/CMPCON.1995.512398"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB12","doi-asserted-by":"crossref","unstructured":"L. Liu, Cache design with partial address matching, in: Proceedings of the MICRO'27, 1994, pp. 128\u2013136","DOI":"10.1145\/192724.192742"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB13","unstructured":"L. Liu, History table for set prediction for accessing a set-associative cache, US Patent 5,418,922, May 1995"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB14","doi-asserted-by":"crossref","unstructured":"J. Peir, W. Hsu, H. Young, S. Ong, Improving cache performance with balanced tag and data paths, in: Proceedings of the Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, 1996, pp. 268\u2013278","DOI":"10.1145\/237090.237202"},{"issue":"2","key":"10.1016\/S1383-7621(99)00021-1_BIB15","doi-asserted-by":"crossref","first-page":"100","DOI":"10.1109\/12.752651","article-title":"Functional implementation techniques for CPU cache memories","volume":"48","author":"Peir","year":"1999","journal-title":"IEEE Trans. Comput., Special Issue on Cache Memory"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB16","doi-asserted-by":"crossref","unstructured":"A. Seznec, DASC cache, in: Proceedings of the First Symposium on High-Performance Computer Architecture, 1995, pp. 134\u2013143","DOI":"10.1109\/HPCA.1995.386548"},{"issue":"6","key":"10.1016\/S1383-7621(99)00021-1_BIB17","doi-asserted-by":"crossref","first-page":"700","DOI":"10.1109\/12.2208","article-title":"Cache operations by MRU change","volume":"C-37","author":"So","year":"1988","journal-title":"IEEE Trans. Comput."},{"key":"10.1016\/S1383-7621(99)00021-1_BIB18","unstructured":"System Performance Evaluation Cooperative, SPEC News-letter, 1990"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB19","unstructured":"TPC Council, TPC Benchmark C, Standard Specification, Rev. 3.0, February 1995"},{"key":"10.1016\/S1383-7621(99)00021-1_BIB20","unstructured":"S. Wilton, N. Jouppi, An enhanced access and cycle time model for on-chip caches, DEC WRL Research Report 93\/5, July 1994"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762199000211?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762199000211?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2020,1,8]],"date-time":"2020-01-08T08:14:40Z","timestamp":1578471280000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762199000211"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,3]]},"references-count":20,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2000,3]]}},"alternative-id":["S1383762199000211"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(99)00021-1","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2000,3]]}}}