{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,2]],"date-time":"2022-04-02T06:05:10Z","timestamp":1648879510009},"reference-count":22,"publisher":"Elsevier BV","issue":"9","license":[{"start":{"date-parts":[[2000,7,1]],"date-time":"2000-07-01T00:00:00Z","timestamp":962409600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2000,7]]},"DOI":"10.1016\/s1383-7621(99)00029-6","type":"journal-article","created":{"date-parts":[[2003,4,7]],"date-time":"2003-04-07T18:33:56Z","timestamp":1049740436000},"page":"749-764","source":"Crossref","is-referenced-by-count":0,"title":["Register bypassing in an asynchronous superscalar processor"],"prefix":"10.1016","volume":"46","author":[{"given":"S.J","family":"Davis","sequence":"first","affiliation":[]},{"given":"C.J","family":"Elston","sequence":"additional","affiliation":[]},{"given":"P.A","family":"Findlay","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(99)00029-6_BIB1","series-title":"Introduction to VLSI Systems","first-page":"218","article-title":"System timing","author":"Seitz","year":"1980"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB2","doi-asserted-by":"crossref","unstructured":"C.J. Elston, Hades: an asynchronous superscalar processor, Ph.D. Thesis, University of Hertfordshire, 1997","DOI":"10.1049\/ic:19960255"},{"issue":"12","key":"10.1016\/S1383-7621(99)00029-6_BIB3","doi-asserted-by":"crossref","first-page":"65","DOI":"10.1109\/2.62094","article-title":"An overview of common benchmarks","volume":"23","author":"Weicker","year":"1990","journal-title":"Computer (IEEE)"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB4","unstructured":"D.W. Wall, Personal communication, 1991"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB5","doi-asserted-by":"crossref","unstructured":"S.B. Furber, P. Day, J.D. Garside, N.C. Paver, J.V. Woods, AMULET1: a micropipelined ARM, Proceedings of CompCon\u201994, IEEE Press, San Francisco, March 1994, pp. 476\u2013485","DOI":"10.1109\/CMPCON.1994.282880"},{"issue":"6","key":"10.1016\/S1383-7621(99)00029-6_BIB6","doi-asserted-by":"crossref","first-page":"720","DOI":"10.1145\/63526.63532","article-title":"Micropipelines","volume":"32","author":"Sutherland","year":"1989","journal-title":"Communications of the ACM"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB7","unstructured":"S.B. Furber, P. Day, J.D. Garside, N.C. Paver, S. Temple, AMULET2e, EMSYS \u201996 \u2013 OMI Sixth Annual Conference, IOS, Berlin, 23\u201325 September 1996"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB8","doi-asserted-by":"crossref","unstructured":"R.F. Sproull, I.E. Sutherland, C.E. Molnar, CounterFlow Pipeline Processor architecture, Technical Report SMLI TR-94-25, Sun Microsystems Laboratories, 1994","DOI":"10.1109\/MDT.1994.303847"},{"issue":"5","key":"10.1016\/S1383-7621(99)00029-6_BIB9","doi-asserted-by":"crossref","first-page":"259","DOI":"10.1049\/ip-cdt:19960657","article-title":"Rotary pipeline processors","volume":"143","author":"Moore","year":"1996","journal-title":"IEE Proceedings, Computers and Digital Techniques"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB10","unstructured":"P.B. Endicott, SCALP, Ph.D. Thesis, University of Manchester, 1996"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB11","first-page":"692","article-title":"Move: a framework for high-performance processor design","volume":"7","author":"Corporaal","year":"1991","journal-title":"Supercomputing"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB12","doi-asserted-by":"crossref","unstructured":"J. Hoogerbrugge, H. Corporaal, Register file port requirements of transport triggered architectures, Micro 27, ACM, San Jose, CA, November 1994, pp. 191\u2013195","DOI":"10.1109\/MICRO.1994.717458"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB13","doi-asserted-by":"crossref","unstructured":"S.V. Morton, S.S. Appleton, M.J. Liebelt, ECSTAC: a fast asynchronous microprocessor, Second Working Conference on Asynchronous Design Methodologies, IEEE Press, London, UK, 30\u201331 May 1995, pp. 180\u2013189","DOI":"10.1109\/WCADM.1995.514655"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB14","doi-asserted-by":"crossref","unstructured":"A. Martin, S. Burns, T. Lee, D. Borkovic, P. Hazewindus, The Design of an asynchronous microprocessor, Technical Report CS-TR-89-02, Caltech, 1989","DOI":"10.21236\/ADA447727"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB15","doi-asserted-by":"crossref","first-page":"259","DOI":"10.1016\/0165-6074(93)90264-L","article-title":"ALU design and processor branch architecture","volume":"36","author":"Steven","year":"1993","journal-title":"Microprocessing and Microprogramming"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB16","doi-asserted-by":"crossref","unstructured":"N. Paver, P. Day, S.B. Furber, J.D. Garside, J.V. Wood, Register locking in an asynchronous microprocessor, ICCD 92: IEEE International Conference on Computer Design, October 1992, pp. 351\u2013355","DOI":"10.1109\/ICCD.1992.276287"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB17","unstructured":"D.A. Patterson, J.L. Hennessy, Computer Architecture: a Quantitative Approach, 2nd ed., Morgan Kaufmann, Los Altos, CA, 1996, pp. 146\u2013155"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB18","doi-asserted-by":"crossref","unstructured":"M. Franklin, G.S. Sohi, Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors, Micro25, ACM, Portland, OR, December 1992, pp. 236\u2013245","DOI":"10.1109\/MICRO.1992.697025"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB19","series-title":"Communicating Sequential Processes","author":"Hoare","year":"1985"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB20","unstructured":"IEEE Standard VHDL reference manual, IEEE Std 1076-1987"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB21","doi-asserted-by":"crossref","DOI":"10.1049\/ip-cdt:19951622","article-title":"Using a resource limited instruction scheduler to evaluate the iHARP processor","author":"Steven","year":"1995","journal-title":"IEE Proceedings, Computers and Digital Techniques"},{"key":"10.1016\/S1383-7621(99)00029-6_BIB22","doi-asserted-by":"crossref","first-page":"391","DOI":"10.1016\/S0141-9331(96)01101-5","article-title":"A Superscalar architecture to exploit instruction level parallelism","volume":"20","author":"Steven","year":"1997","journal-title":"Microprocessors and Microsystems"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762199000296?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S1383762199000296?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2020,2,5]],"date-time":"2020-02-05T04:19:39Z","timestamp":1580876379000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S1383762199000296"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,7]]},"references-count":22,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2000,7]]}},"alternative-id":["S1383762199000296"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(99)00029-6","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2000,7]]}}}