{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,12,7]],"date-time":"2024-12-07T05:15:56Z","timestamp":1733548556993,"version":"3.30.1"},"reference-count":25,"publisher":"Elsevier BV","issue":"10","license":[{"start":{"date-parts":[[2000,7,1]],"date-time":"2000-07-01T00:00:00Z","timestamp":962409600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2000,7]]},"DOI":"10.1016\/s1383-7621(99)00048-x","type":"journal-article","created":{"date-parts":[[2003,4,7]],"date-time":"2003-04-07T18:33:56Z","timestamp":1049740436000},"page":"903-918","source":"Crossref","is-referenced-by-count":0,"title":["Broadcast directory: A scalable cache coherent architecture for mesh-connected multiprocessors"],"prefix":"10.1016","volume":"46","author":[{"given":"Yunseok","family":"Rhee","sequence":"first","affiliation":[]},{"given":"Joonwon","family":"Lee","sequence":"additional","affiliation":[]}],"member":"78","reference":[{"doi-asserted-by":"crossref","unstructured":"M. Dubois, C. Scheurich, F. Briggs, Synchronization, coherence and event ordering in multiprocessors, Computer 21 (Feb) (1998) 9\u201321","key":"10.1016\/S1383-7621(99)00048-X_BIB1","DOI":"10.1109\/2.15"},{"issue":"2","key":"10.1016\/S1383-7621(99)00048-X_BIB2","doi-asserted-by":"crossref","first-page":"121","DOI":"10.1145\/356810.356813","article-title":"Experience using multiprocessor systems: a status report","volume":"12","author":"Jones","year":"1980","journal-title":"ACM Computing Surveys"},{"year":"1992","author":"Dubois","series-title":"Sclable shared-memory multiprocessor","key":"10.1016\/S1383-7621(99)00048-X_BIB3"},{"issue":"4","key":"10.1016\/S1383-7621(99)00048-X_BIB4","doi-asserted-by":"crossref","first-page":"273","DOI":"10.1145\/6513.6514","article-title":"An evaluation of cache coherence solutions in shared-bus multiprocessors","volume":"4","author":"Archibald","year":"1986","journal-title":"ACM Transactions on Computer Systems"},{"doi-asserted-by":"crossref","unstructured":"D. Chaiken, C. Fields, K. Kurihara, A. Agarwal, Directory-based cache coherence in large-scale multiprocessors, IEEE Computer, June 1990, pp. 49\u201358","key":"10.1016\/S1383-7621(99)00048-X_BIB5","DOI":"10.1109\/2.55500"},{"doi-asserted-by":"crossref","unstructured":"L.M. Censier, P. Feautrier, A new solution to cache problems in multicache systems, IEEE Transactions on Computers C-27 (1978) 1112\u20131118","key":"10.1016\/S1383-7621(99)00048-X_BIB6","DOI":"10.1109\/TC.1978.1675013"},{"doi-asserted-by":"crossref","unstructured":"A. Agarwal, R. Simoni, J. Hennessy, M. Horowitz, An evaluation of directory schemes for cache coherence, in: Proceedings of the 15th International Symposium on Computer Architecture, June 1988","key":"10.1016\/S1383-7621(99)00048-X_BIB7","DOI":"10.1109\/ISCA.1988.5238"},{"unstructured":"A. Gupta, W.-D. Weber, T. Mowry, Reducing memory and traffic requirements for scalable directory-based cache coherence schemes, in: Proceedings of International Conference on Parallel Processing, 1990","key":"10.1016\/S1383-7621(99)00048-X_BIB8"},{"doi-asserted-by":"crossref","unstructured":"D. Chaiken, J. Kubiatowicz, A. Agarwal, Limitless directories: a scalable cache coherence scheme, in: Proceedings of International Conference on Architectural Support for Programming Language and Operating Systems, vol. IV, April 1991","key":"10.1016\/S1383-7621(99)00048-X_BIB9","DOI":"10.1145\/106972.106995"},{"doi-asserted-by":"crossref","unstructured":"S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, A. Gupta, The SPLASH-2 programs: characterization and methodological consideration, in: Proceedings of the 22nd International Symposium on Computer Architecture, June 1995, pp. 24\u201336","key":"10.1016\/S1383-7621(99)00048-X_BIB10","DOI":"10.1145\/223982.223990"},{"year":"1993","author":"Hwang","series-title":"Advanced Computer Architecture: Parallelism, Scalability, Programmability","key":"10.1016\/S1383-7621(99)00048-X_BIB11"},{"doi-asserted-by":"crossref","unstructured":"D. Dai, D.K. Panda, Reducing cache invalidation overheads in wormhole routed dsms using multidestination message passing, in: Proceedings of International Conference on Parallel Processing, vol. 1, August 1996, pp. 138\u2013145","key":"10.1016\/S1383-7621(99)00048-X_BIB12","DOI":"10.1109\/ICPP.1996.537154"},{"doi-asserted-by":"crossref","unstructured":"W.D. Weber, A. Gupta, Analysis of cache invalidation patterns in multiprocessors, in: Proceedings of the International Conference on Architectural Support for Programming Language and Operating Systems, vol. III, April 1989, pp. 243\u2013256","key":"10.1016\/S1383-7621(99)00048-X_BIB13","DOI":"10.1145\/70082.68205"},{"doi-asserted-by":"crossref","unstructured":"D.V. James, A.T. Laundrie, S. Gjessing, G.S. Sohi, Scalable coherence interface, IEEE Computer 23 (June) (1990) 74\u201377","key":"10.1016\/S1383-7621(99)00048-X_BIB14","DOI":"10.1109\/2.55503"},{"doi-asserted-by":"crossref","unstructured":"P.K. McKinley, D.F. Robinson, Collective communication in wormhole-routed massively parallel computers, IEEE Computer, December 1995, pp. 39\u201350","key":"10.1016\/S1383-7621(99)00048-X_BIB15","DOI":"10.1109\/2.476198"},{"year":"1992","author":"J\u00e1J\u00e1","series-title":"An Introduction to Parallel Algorithms","key":"10.1016\/S1383-7621(99)00048-X_BIB16"},{"issue":"3","key":"10.1016\/S1383-7621(99)00048-X_BIB17","doi-asserted-by":"crossref","first-page":"187","DOI":"10.1007\/BF01660031","article-title":"The torus routing chip","volume":"1","author":"Dally","year":"1986","journal-title":"Journal of Distributed Computing"},{"doi-asserted-by":"crossref","unstructured":"D. Lenoski, J. Laudon, K. Gharachorloo, W.D. Weber, A. Gupta, J. Hennesy, M. Horowitz, M. Lam, The Stanford DASH multiprocessor, IEEE Computer, March 1992, pp. 63\u201379","key":"10.1016\/S1383-7621(99)00048-X_BIB18","DOI":"10.1109\/2.121510"},{"doi-asserted-by":"crossref","unstructured":"A. Agarwal et al., The MIT Alewife machine: a large-scale distributed-memory multiprocessor, in: Proceedings of the Workshop on Scalable Shared Memory Multiprocessors, 1991","key":"10.1016\/S1383-7621(99)00048-X_BIB19","DOI":"10.1007\/978-1-4615-3604-8_13"},{"unstructured":"I.S.S. Division, Paragon XP\/S Product Overview, Intel Corporation, 1990","key":"10.1016\/S1383-7621(99)00048-X_BIB20"},{"doi-asserted-by":"crossref","unstructured":"W.J. Dally, C.L. Seitz, Deadlock-free message routing in multiprocessor interconnection network, IEEE Transactions on Computer C-36 (May) (1987) 547\u2013553","key":"10.1016\/S1383-7621(99)00048-X_BIB21","DOI":"10.1109\/TC.1987.1676939"},{"doi-asserted-by":"crossref","unstructured":"J.E. Veenstra, R.J. Fowler, MINT tutorial and user manual, Technical report 452, University of Rochester, August 1994","key":"10.1016\/S1383-7621(99)00048-X_BIB22","DOI":"10.1109\/MASCOT.1994.284422"},{"doi-asserted-by":"crossref","unstructured":"L. Lamport, How to make a multiprocessor computer that correctly executes multiprocess programs, IEEE Transactions on Computer C-28 (September) (1979)","key":"10.1016\/S1383-7621(99)00048-X_BIB23","DOI":"10.1109\/TC.1979.1675439"},{"doi-asserted-by":"crossref","unstructured":"S.V. Adve, M.D. Hill, Weak ordering \u2013 a new definition, in: Proceedings of the 17th International Symposium on Computer Architecture, May 1990","key":"10.1016\/S1383-7621(99)00048-X_BIB24","DOI":"10.1145\/325164.325100"},{"doi-asserted-by":"crossref","unstructured":"T.E. Anderson, The performance implications of spin lock alternatives for shared-memory multiprocessors, IEEE Transactions on Parallel and Distributed Systems 1 (January) (1990) 6\u201316","key":"10.1016\/S1383-7621(99)00048-X_BIB25","DOI":"10.1109\/71.80120"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S138376219900048X?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S138376219900048X?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2024,12,6]],"date-time":"2024-12-06T17:51:45Z","timestamp":1733507505000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S138376219900048X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2000,7]]},"references-count":25,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2000,7]]}},"alternative-id":["S138376219900048X"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(99)00048-x","relation":{},"ISSN":["1383-7621"],"issn-type":[{"type":"print","value":"1383-7621"}],"subject":[],"published":{"date-parts":[[2000,7]]}}}