{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,16]],"date-time":"2026-03-16T10:17:04Z","timestamp":1773656224796,"version":"3.50.1"},"reference-count":32,"publisher":"Elsevier BV","issue":"14-15","license":[{"start":{"date-parts":[[2002,8,1]],"date-time":"2002-08-01T00:00:00Z","timestamp":1028160000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.elsevier.com\/tdm\/userlicense\/1.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Systems Architecture"],"published-print":{"date-parts":[[2002,8]]},"DOI":"10.1016\/s1383-7621(02)00067-x","type":"journal-article","created":{"date-parts":[[2002,8,26]],"date-time":"2002-08-26T21:15:57Z","timestamp":1030396557000},"page":"1043-1064","source":"Crossref","is-referenced-by-count":38,"title":["Reconfigurable models of finite state machines and their implementation in FPGAs"],"prefix":"10.1016","volume":"47","author":[{"given":"V.","family":"Sklyarov","sequence":"first","affiliation":[]}],"member":"78","reference":[{"key":"10.1016\/S1383-7621(02)00067-X_BIB1","doi-asserted-by":"crossref","unstructured":"J. Rabaey, Silicon Platforms for the Next Generation Wireless Systems\u2013\u2013What Role Does Reconfigurable Hardware Play? in: Proceeding of FPL'2000, Villach, Austria, 2000, pp. 277\u2013285","DOI":"10.1007\/3-540-44614-1_31"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB2","doi-asserted-by":"crossref","unstructured":"P. Schaumont, I. Verbauwhede, K. Keutzer, M. Sarrafzadeh, A Quick Safari through the Reconfiguration Jungle, in: Proceedings of the 38th Design Automation Conference, Las Vegas, 2001, pp. 172\u2013177","DOI":"10.1145\/378239.378404"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB3","doi-asserted-by":"crossref","unstructured":"M. Koster, J. Teich, (Self-)reconfigurable Finite State Machines: Theory and Implementation, in: Proceedings of DATE'2002, Paris, 2002, pp. 559\u2013566","DOI":"10.1109\/DATE.2002.998356"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB4","doi-asserted-by":"crossref","unstructured":"I. Skliarova, A. Ferrari, Design and Implementation of Reconfigurable Processor for Problems of Combinatorial Computations, in: Proceedings of EUROMICRO Symposium on Digital Systems Design, Warsaw, 2001, pp. 112\u2013119","DOI":"10.1109\/DSD.2001.952250"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB5","unstructured":"Available from <http:\/\/www.ecs.umass.edu\/vspgroup\/burleson\/WWW\/reconfig.html>"},{"issue":"2","key":"10.1016\/S1383-7621(02)00067-X_BIB6","doi-asserted-by":"crossref","first-page":"222","DOI":"10.1109\/92.766749","article-title":"Hierarchical finite-state machines and their use for digital control","volume":"7","author":"Sklyarov","year":"1999","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB7","doi-asserted-by":"crossref","unstructured":"V. Sklyarov, An Evolutionary Algorithm for the Synthesis of RAM-based FSMs, in: Proceedings of the 15th International Conference on Industrial and Engineering Applications of Artificial Intelligence and Expert Systems, Cairns, June, 2002","DOI":"10.1007\/3-540-48035-8_11"},{"issue":"April","key":"10.1016\/S1383-7621(02)00067-X_BIB8","first-page":"1","article-title":"Hardware\/software modeling of FPGA-based systems","volume":"17","author":"Sklyarov","year":"2002","journal-title":"Parallel Algorithms and Applications"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB9","doi-asserted-by":"crossref","unstructured":"A. Dollas, K. Papademetriou, N. Aslanides, T. Kean, A Reconfigurable Embedded Input Device for Kinetically Challenged Persons, Springer-Verlag, Lecture Notes in Computer Science 2147, 2001","DOI":"10.1007\/3-540-44687-7_34"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB10","unstructured":"A. Oliveira, Models, Methods and Tools for Implementation of Virtual Control Units, M.Sc. Thesis, Aveiro, Portugal, 2000, p. 353"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB11","unstructured":"A. Adrego da Rocha, Synthesis and Simulation of Reprogrammable Control Units from Hierarchical Specification, Ph.D. Thesis, Aveiro, Portugal, 1999, p. 202"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB12","unstructured":"A. Melo, Specification, Optimization and Test of Hierarchical Control Algorithms, M.Sc. Thesis, Aveiro, Portugal, 2000, p. 155"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB13","doi-asserted-by":"crossref","unstructured":"V. Sklyarov, R. Monteiro, N. Lau, et al., Integrated Development Environment for Logic Synthesis Based on Dynamically Reconfigurable FPGAs, in: Proceeding of FPL'98, Tallinn, 1998, pp. 19\u201328","DOI":"10.1007\/BFb0055229"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB14","doi-asserted-by":"crossref","unstructured":"V. Sklyarov, Logic Synthesis of Reconfigurable Control Circuits Based on Mutually Exclusive Reprogrammable Elements, in: Proceeding of XI Brazilian Symposium on Integrated Circuit Design\u2013\u2013SBCCI98, Rio de Janeiro, 1998, pp. 221\u2013224","DOI":"10.1109\/SBCCI.1998.715446"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB15","unstructured":"A. Oliveira, N. Lau, V. Sklyarov, Synthesis of VHDL Code from the Hierarchical Specification of Control Circuits for Dynamically Reconfigurable FPGAs, in: Proceedings of VHDL International User Forum, Orlando, USA, 1998"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB16","series-title":"Logic Synthesis for Control Automata","author":"Baranov","year":"1994"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB17","unstructured":"A. Zakrevskij, V. Sklyarov, The Specification and Design of Parallel Logical Control Devices, in: Proceedings of PDPTA'2000, June, Las Vegas, USA, 2000, pp. 1635\u20131641"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB18","doi-asserted-by":"crossref","unstructured":"V. Sklyarov, Synthesis and Implementation of RAM-based Finite State Machines in FPGAs, in: Proceedings of FPL'2000, Villach, Austria, August, 2000, pp. 718\u2013728","DOI":"10.1007\/3-540-44614-1_76"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB19","unstructured":"V. Sklyarov, Graphical Description and Hardware Implementation of Parallel Control Algorithms, in: Proceedings of PDPTA'99, June, Las Vegas, USA, 1999, pp. 1390\u20131396"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB20","series-title":"Logical Synthesis of Cascade Networks","author":"Zakrevskij","year":"1981"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB21","unstructured":"Xilinx Development System. Foundation Series. Version 3.1, 2000"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB22","doi-asserted-by":"crossref","unstructured":"V. Sklyarov, Synthesis of Control Circuits with Dynamically Modifiable Behavior on the Basis of Statically Reconfigurable FPGAs, in: Proceedings of the 13th Symposium on Integrated Circuits and Systems Design: SBCCI2000, Manaus, Brazil, 18\u201324 September, 2000, pp. 353\u2013358","DOI":"10.1109\/SBCCI.2000.876054"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB23","unstructured":"N. Lau, V. Sklyarov, An Algebra of FPGA Configurations, in: Proceedings of DDECS'2001, Gyor, Hungary, 2001, pp. 187\u2013194"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB24","unstructured":"Available from <http:\/\/webct.ua.pt> \u201c1\u00b0 Semester\u201d a discipline \u201cSistemas Digitais Avan\u00e7ados\u201d"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB25","unstructured":"J.M. Silva, P. Bjesse, W. Kunz, Boolean Satisfiability Solving and its Application in Equivalence and Model Checking, ICCAD 2001, Tutorial, San Jose, 2001"},{"issue":"2","key":"10.1016\/S1383-7621(02)00067-X_BIB26","first-page":"261","article-title":"Combinatorial problems over logical matrices in logic design and artificial intelligence","volume":"2","author":"Zakrevskij","year":"1998","journal-title":"Electr\u00f3nica e Telecomunica\u00e7\u00f5es"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB27","doi-asserted-by":"crossref","unstructured":"M. Platzner, Reconfigurable Accelerators for Combinatorial Problems, IEEE Computer, April 2000, pp. 58\u201360","DOI":"10.1109\/2.839322"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB28","unstructured":"J.T. de Sousa et al., A Configware\/Software Approach to SAT Solving, in: Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines\u2013\u2013FCCM'2001"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB29","unstructured":"V. Sklyarov, I. Skliarova, A. Ferrari, Hierarchical Specification and Implementation of Combinatorial Algorithms Based on RHS Model, in: Proceedings of the XVI Conference on Design of Circuits and Integrated Systems\u2013\u2013DCIS2001, Porto, 2001, pp. 486\u2013491"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB30","unstructured":"A. Zakrevskij, Combinatorial theory of logical design, Automatics and computer techniques no. 2 (1990) 68\u201379"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB31","unstructured":"B. Oestereich, Developing software with UML, Addison-Wesley, 1999"},{"key":"10.1016\/S1383-7621(02)00067-X_BIB32","unstructured":"V.Sklyarov, Modela\u00e7\u00e3o em C++, S\u0131\u0301ntese e Implementa\u00e7\u00e3o de Circuitos Digitais com base em FPGA, Electr\u00f3nica e Telecomunica\u00e7\u00f5es, January, 2002"}],"container-title":["Journal of Systems Architecture"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S138376210200067X?httpAccept=text\/xml","content-type":"text\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/api.elsevier.com\/content\/article\/PII:S138376210200067X?httpAccept=text\/plain","content-type":"text\/plain","content-version":"vor","intended-application":"text-mining"}],"deposited":{"date-parts":[[2019,4,10]],"date-time":"2019-04-10T17:25:10Z","timestamp":1554917110000},"score":1,"resource":{"primary":{"URL":"https:\/\/linkinghub.elsevier.com\/retrieve\/pii\/S138376210200067X"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2002,8]]},"references-count":32,"journal-issue":{"issue":"14-15","published-print":{"date-parts":[[2002,8]]}},"alternative-id":["S138376210200067X"],"URL":"https:\/\/doi.org\/10.1016\/s1383-7621(02)00067-x","relation":{},"ISSN":["1383-7621"],"issn-type":[{"value":"1383-7621","type":"print"}],"subject":[],"published":{"date-parts":[[2002,8]]}}}