{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T13:00:19Z","timestamp":1761310819890,"version":"build-2065373602"},"reference-count":26,"publisher":"Cambridge University Press (CUP)","issue":"4","license":[{"start":{"date-parts":[[2025,9,5]],"date-time":"2025-09-05T00:00:00Z","timestamp":1757030400000},"content-version":"unspecified","delay-in-days":66,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":["cambridge.org"],"crossmark-restriction":true},"short-container-title":["Theory and Practice of Logic Programming"],"published-print":{"date-parts":[[2025,7]]},"abstract":"<jats:title>Abstract<\/jats:title>\n                  <jats:p>In the design of integrated circuits, one critical metric is the maximum delay introduced by combinational modules within the circuit. This delay is crucial because it represents the time required to perform a computation: in an Arithmetic Logic Unit, it represents the maximum time taken by the circuit to perform an arithmetic operation. When such a circuit is part of a larger, synchronous system, like a CPU, the maximum delay directly impacts the maximum clock frequency of the entire system. Typically, hardware designers use static timing analysis to compute an upper bound of the maximum delay because it can be determined in polynomial time. However, relying on this upper bound can lead to suboptimal processor speeds, thereby missing performance opportunities. In this work, we tackle the challenging task of computing the actual maximum delay, rather than an approximate value. Since the problem is computationally hard, we model it in answer set programming (ASP), a logic language featuring extremely efficient solvers. We propose non-trivial encodings of the problem into ASP. Experimental results show that ASP is a viable solution to address complex problems in hardware design.<\/jats:p>","DOI":"10.1017\/s1471068425100288","type":"journal-article","created":{"date-parts":[[2025,9,5]],"date-time":"2025-09-05T06:06:40Z","timestamp":1757052400000},"page":"522-539","update-policy":"https:\/\/doi.org\/10.1017\/policypage","source":"Crossref","is-referenced-by-count":0,"title":["Fine-Grained Timing Analysis of Digital Integrated Circuits in Answer Set Programming"],"prefix":"10.1017","volume":"25","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2390-0629","authenticated-orcid":false,"given":"ALESSANDRO","family":"BERTAGNON","sequence":"first","affiliation":[{"name":"University of Ferrara"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"MARCELLO","family":"DALPASSO","sequence":"additional","affiliation":[{"name":"DEI - University of Padova"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"MICHELE","family":"FAVALLI","sequence":"additional","affiliation":[{"name":"University of Ferrara"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7433-5899","authenticated-orcid":false,"given":"MARCO","family":"GAVANELLI","sequence":"additional","affiliation":[{"name":"University of Ferrara"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"56","published-online":{"date-parts":[[2025,9,5]]},"reference":[{"key":"S1471068425100288_ref1","doi-asserted-by":"crossref","unstructured":"Agrawal, V. 1982. Synchronous path analysis in MOS circuit simulator. In 19th Design Automation Conference, 629\u2013635.","DOI":"10.1109\/DAC.1982.1585562"},{"key":"S1471068425100288_ref5","doi-asserted-by":"publisher","DOI":"10.3233\/IA-240032"},{"key":"S1471068425100288_ref3","doi-asserted-by":"crossref","unstructured":"Andres, B. , Sauer, M. , Gebser, M. , Schubert, T. , Becker, B. and Schaub, T. 2013b. Accurate computation of sensitizable paths using answer set programming. In Logic Programming and Nonmonotonic Reasoning, 12th International Conference, LPNMR 2013, Corunna, Spain, September 15-19, 2013. Proceedings, P. Cabalar and T. C. Son, Eds. Springer, vol. 8148, 92\u2013101.","DOI":"10.1007\/978-3-642-40564-8_10"},{"key":"S1471068425100288_ref4","doi-asserted-by":"publisher","DOI":"10.1093\/logcom\/exae042"},{"key":"S1471068425100288_ref11","doi-asserted-by":"publisher","DOI":"10.1609\/aimag.v37i3.2678"},{"key":"S1471068425100288_ref10","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-010-5146-y"},{"key":"S1471068425100288_ref12","doi-asserted-by":"crossref","unstructured":"Gavanelli, M. , Nonato, M. , Peano, A. and Bertozzi, D. 2017. Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (application paper). Theory and Practice of Logic Programming 17, 800\u2013818.","DOI":"10.1017\/S1471068417000424"},{"key":"S1471068425100288_ref19","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(94)90018-3"},{"volume-title":"Static Timing Analysis for Nanometer Designs. A Practical Approach","year":"2009","author":"Chadha","key":"S1471068425100288_ref8"},{"key":"S1471068425100288_ref14","unstructured":"Gelfond, M. and Lifschitz, V. (1988) The stable model semantics for logic programming. In International Conference on Logic Programming, R. A. Kowalski and K. A. Bowen, Eds."},{"key":"S1471068425100288_ref18","doi-asserted-by":"crossref","unstructured":"Janhunen, T. , Kaminski, R. , Ostrowski, M. , Schellhorn, S. , Wanko, P. and Schaub, T. 2017. Clingo goes linear constraints over reals and integers. Theory and Practice of Logic Programming 17, 872\u2013888.","DOI":"10.1017\/S1471068417000242"},{"key":"S1471068425100288_ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-74209-5_17"},{"key":"S1471068425100288_ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2024.3357754"},{"key":"S1471068425100288_ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3372461"},{"key":"S1471068425100288_ref6","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2018.02.010"},{"key":"S1471068425100288_ref9","first-page":"44","volume-title":"RT-Level ITC 99 Benchmarks and First ATPG Results","author":"Corno","year":"2000"},{"key":"S1471068425100288_ref16","doi-asserted-by":"crossref","unstructured":"Hitchcock, R. 1982. Timing verification and the timing analysis program. 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Symposium on Circuits and Systems (ISCAS\u201985)."},{"key":"S1471068425100288_ref26","doi-asserted-by":"crossref","first-page":"385","DOI":"10.1109\/TCAD.2018.2808240","article-title":"Error estimation and error reduction with input-vector profiling for timing speculation in digital circuits","volume":"38","author":"Wang","year":"2019","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"S1471068425100288_ref2","doi-asserted-by":"crossref","unstructured":"Andres, B. , Gebser, M. , Schaub, T. , Haubelt, C. , Reimann, F. and Gla\u00df, M. 2013a. Symbolic system synthesis using answer set programming. In Logic Programming and Nonmonotonic Reasoning, 12th International Conference, LPNMR 2013, Corunna, Spain, September 15-19, 2013. Proceedings, P. Cabalar and T. C. Son, Eds. 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Testing the path delay faults of ISCAS85 circuit c6288. In Proc. 4th Int. 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Published by Cambridge University Press","name":"copyright","label":"Copyright","group":{"name":"copyright_and_licensing","label":"Copyright and Licensing"}},{"value":"This is an Open Access article, distributed under the terms of the Creative Commons Attribution licence (https:\/\/creativecommons.org\/licenses\/by\/4.0\/), which permits unrestricted re-use, distribution and reproduction, provided the original article is properly cited.","name":"license","label":"License","group":{"name":"copyright_and_licensing","label":"Copyright and Licensing"}},{"value":"This content has been made available to all.","name":"free","label":"Free to read"}]}}