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Increasing the indium fraction in the IGO channel improved ION but simultaneously caused a pronounced negative VTH shift, revealing an observed trade-off in composition-based channel engineering. To circumvent this limitation, the SiO2 spacer thickness was scaled from 100 to 30 nm while maintaining the optimized IGO 6:3 channel composition. For IGO FETs with a gate length of 40 nm, the average ION increased from 1.24 \u00b1 0.54 to 9.5 \u00b1 1.94 \u03bcA as the spacer thickness was reduced from 100 to 30 nm, without inducing a negative VTH shift. For twenty 30-nm-spacer devices, the average VTH and subthreshold swing were 0.29 \u00b1 0.05 V and 71.4 \u00b1 4 mV\/dec, respectively, with an apparent drain-induced barrier lowering (DIBL) factor of 3.7 mV\/V. Y-function analysis, temperature-dependent measurements, and Technology Computer-Aided Design (TCAD) simulations revealed that the performance enhancement originated from reduced access resistance and electrostatic modulation of the source-side access region, while no statistically distinct spacer-dependent change in the effective source-side injection barrier was resolved. The optimized device also exhibited VTH shifts of only +79 and \u201326 mV under positive and negative bias-temperature stress, respectively, at 95 \u00b0C for 3600 s under effective gate fields of \u00b13 MV\/cm, while the VGAA-based two-transistor zero-capacitor dynamic random-access memory (2T0C DRAM) cell exhibited a retention time exceeding 100 s. These results establish spacer-defined offset engineering as an effective structural design approach for oxide-semiconductor memory transistors that require both high ION and stable VTH operation.<\/jats:p>","DOI":"10.1021\/acsami.6c13898","type":"journal-article","created":{"date-parts":[[2026,10,1]],"date-time":"2026-10-01T18:01:29Z","timestamp":1790877689000},"page":"55124-55136","source":"Crossref","is-referenced-by-count":0,"title":["Breaking the Drivability-Threshold-Voltage Trade-off in 40 nm Vertical Gate-All-Around Oxide FETs via Spacer-Defined Offset Engineering"],"prefix":"10.1021","volume":"18","author":[{"given":"Seong Hun","family":"Yoon","sequence":"first","affiliation":[{"name":"Hanyang University , , ,","place":["Seoul, Republic of Korea, 04763"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jaehyun","family":"Park","sequence":"additional","affiliation":[{"name":"Hanyang University , , ,","place":["Seoul, Republic of Korea, 04763"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Minsong","family":"Kim","sequence":"additional","affiliation":[{"name":"Hanyang University , , ,","place":["Seoul, Republic of Korea, 04763"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jungho","family":"Lee","sequence":"additional","affiliation":[{"name":"Hanyang University , , ,","place":["Seoul, Republic of Korea, 04763"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jihun","family":"An","sequence":"additional","affiliation":[{"name":"Hanyang University , , ,","place":["Seoul, Republic of Korea, 04763"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3857-1039","authenticated-orcid":true,"given":"Jae Kyeong","family":"Jeong","sequence":"additional","affiliation":[{"name":"Hanyang University , , ,","place":["Seoul, Republic of Korea, 04763"]},{"name":"Hanyang University , , ,","place":["Seoul, Republic of Korea, 04763"]},{"name":"Hanyang University , , ,","place":["Seoul, Republic of Korea, 04763"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"316","published-online":{"date-parts":[[2026,10,1]]},"reference":[{"issue":"20","key":"2026101406072630400_cit1","doi-asserted-by":"publisher","DOI":"10.1002\/adma.202210554","article-title":"True Nonvolatile High-Speed DRAM Cells Using Tailored Ultrathin IGZO","volume":"35","author":"Hu","year":"2023","journal-title":"Adv. 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