{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,15]],"date-time":"2025-08-15T01:22:01Z","timestamp":1755220921049,"version":"3.43.0"},"reference-count":18,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[1997,12,1]],"date-time":"1997-12-01T00:00:00Z","timestamp":880934400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[1997,12,1]],"date-time":"1997-12-01T00:00:00Z","timestamp":880934400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["The Journal of Supercomputing"],"published-print":{"date-parts":[[1997,12]]},"DOI":"10.1023\/a:1007974908210","type":"journal-article","created":{"date-parts":[[2002,12,22]],"date-time":"2002-12-22T07:13:40Z","timestamp":1040541220000},"page":"405-420","source":"Crossref","is-referenced-by-count":0,"title":["A Performance Study on Bounteous Transfer in Multiprocessor Sectored Caches"],"prefix":"10.1007","volume":"11","author":[{"given":"Kuang-Chih","family":"Liu","sequence":"first","affiliation":[]},{"given":"Chung-Ta","family":"King","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"147014_CR1","unstructured":"C. Anderson and J.-L. Baer. Design and Evaluation of a Subblock Cache Coherence Protocol for Bus-Based Multiprocessors. Technical Report 94-05-02, University of Washington, 1994."},{"key":"147014_CR2","doi-asserted-by":"crossref","unstructured":"C. Anderson and J.-L. Baer. Two Techniques for Improving Performance on Bus-based Multiprocessors. In International Symposium on High Performance Computer Architecture, pp. 264\u2013275, 1995.","DOI":"10.1109\/HPCA.1995.386536"},{"key":"147014_CR3","unstructured":"T.-F. Chen. Data Prefetching for High-Performance Processors. Ph.D. thesis, University of Washington, 1993."},{"key":"147014_CR4","doi-asserted-by":"crossref","unstructured":"Y.-S. Chen and M. Dubois. Cache Protocols with Partial Block Invalidations. In Proc. of 7th International Parallel Processing Symposium, pp. 16\u201324, 1993.","DOI":"10.1109\/IPPS.1993.262850"},{"key":"147014_CR5","doi-asserted-by":"crossref","unstructured":"C. Dubnicki and T.-J. LeBlanc. Adjustable Block Size Coherent Caches. In Proc. of 19thAnnual International Symposium on Computer Architecture, pp. 170\u2013180, 1992.","DOI":"10.1109\/ISCA.1992.753314"},{"key":"147014_CR6","doi-asserted-by":"crossref","unstructured":"M. Dubois, J.-C. Wang, L.A. Barroso, K. Lee, and Y.-S. Chen. Delayed Consistency and its Effects on the Miss Rate of Parallel Programs. In Proc. of Supercomputing'91, pp. 197--206, November 1991.","DOI":"10.1145\/125826.125941"},{"key":"147014_CR7","doi-asserted-by":"crossref","unstructured":"M. Dubois, J. Skeppstedt, L. Ricciulli, K. Ramamurthy, and P. Stenstr\u00f6m. The Detection and Elimination of Useless Misses in Multiprocessors. In Proc. of 20th Annual International Symposium on Computer Architecture, pp. 88\u201397, 1993.","DOI":"10.1145\/165123.165145"},{"key":"147014_CR8","doi-asserted-by":"crossref","unstructured":"S. Dwarkadas, P. Keleher, A. L. Cox, and W. Zwaenepoel. Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology. In Proc. of 20th Annual International Symposium on Computer Architecture, pp. 144\u2013155, 1993.","DOI":"10.1145\/165123.165150"},{"key":"147014_CR9","doi-asserted-by":"crossref","unstructured":"J. Goodman. Coherency for Multiprocessor Virtual Caches. In Proc. of 2nd International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 72\u201381, 1987.","DOI":"10.1145\/36206.36186"},{"key":"147014_CR10","doi-asserted-by":"crossref","unstructured":"P.N. Jouppi. Cache Write Policies and Performance. In Proc. of 20th Annual International Symposium on Computer Architecture, pp. 191\u2013201, 1993.","DOI":"10.1145\/165123.165154"},{"key":"147014_CR11","unstructured":"K.-C. Liu and C.-T. King. On the Effectiveness of Sectored Caches in Reducing False Sharing Misses. In Proc. of the 1997 International Conference on Parallel and Distributed Systems (ICPADS'97), Korea, 1997."},{"key":"147014_CR12","doi-asserted-by":"crossref","unstructured":"L. Lamport. How to Make a Multiprocessor Computer That Correctly Executes Multiprocessor Programs. IEEE Transaction on Computers, vol:690-691, 1979.","DOI":"10.1109\/TC.1979.1675439"},{"key":"147014_CR13","unstructured":"A. Nguyen, M. Michael, A. Sharma, and J. Torrellas. The Augmint Multiprocessor Simulation Toolkit for Intel x86 Architectures. In Proceedings of the 1996 IEEE International Conference on Computer Design (ICCD), Austin, TX, October 1996."},{"key":"147014_CR14","doi-asserted-by":"crossref","unstructured":"M. Papamarcos and J. Patel. A Low Overhead Coherence Solution for Multiprocessors with Private Cache Memories. In Proc. of 11th Annual International Symposium on Computer Architecture, pp. 348\u2013354, 1984.","DOI":"10.1145\/800015.808204"},{"key":"147014_CR15","doi-asserted-by":"crossref","unstructured":"O. Temam and Y. Jegou. Using Virtual Lines to Enhance Locality Exploitation. In Proc. of 1994 International Symposium on Supercomputing, pp. 344-353, 1994.","DOI":"10.1145\/181181.181559"},{"key":"147014_CR16","doi-asserted-by":"crossref","unstructured":"M. Toma\u0161evi\u0107 and V. Milutinovi\u0107. A Simulation Study of Snoopy Cache Coherence Protocols. In Proc. of 25th Hawaii International Conference on System Sciences, pp. 427\u2013436, 1992.","DOI":"10.1109\/HICSS.1992.183192"},{"key":"147014_CR17","doi-asserted-by":"crossref","unstructured":"S.C. Woo, M. Ohara, E. Torrie, J.P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In Proc. of 22nd Annual International Symposium on Computer Architecture, pp. 24\u201336, 1995.","DOI":"10.1145\/223982.223990"},{"key":"147014_CR18","unstructured":"J. Zalewski. Advanced Multimicroprocessor Bus Architectures, IEEE Computer Society Press, 1995."}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1007974908210.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1023\/A:1007974908210\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1023\/A:1007974908210.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,8]],"date-time":"2025-08-08T05:25:17Z","timestamp":1754630717000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1023\/A:1007974908210"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[1997,12]]},"references-count":18,"journal-issue":{"issue":"4","published-print":{"date-parts":[[1997,12]]}},"alternative-id":["147014"],"URL":"https:\/\/doi.org\/10.1023\/a:1007974908210","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"type":"print","value":"0920-8542"},{"type":"electronic","value":"1573-0484"}],"subject":[],"published":{"date-parts":[[1997,12]]}}}